apm,xgene-edac.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/edac/apm,xgene-edac.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: APM X-Gene SoC EDAC
  8
  9maintainers:
 10  - Khuong Dinh <khuong@os.amperecomputing.com>
 11
 12description: >
 13  EDAC node is defined to describe on-chip error detection and correction.
 14
 15  The following error types are supported:
 16
 17    memory controller  - Memory controller
 18    PMD (L1/L2)        - Processor module unit (PMD) L1/L2 cache
 19    L3                 - L3 cache controller
 20    SoC                - SoC IPs such as Ethernet, SATA, etc
 21
 22properties:
 23  compatible:
 24    const: apm,xgene-edac
 25
 26  reg:
 27    items:
 28      - description: CPU bus (PCP) resource
 29
 30  '#address-cells':
 31    const: 2
 32
 33  '#size-cells':
 34    const: 2
 35
 36  ranges: true
 37
 38  interrupts:
 39    description: Interrupt-specifier for MCU, PMD, L3, or SoC error IRQ(s).
 40    items:
 41      - description: MCU error IRQ
 42      - description: PMD error IRQ
 43      - description: L3 error IRQ
 44      - description: SoC error IRQ
 45    minItems: 1
 46
 47  regmap-csw:
 48    description: Regmap of the CPU switch fabric (CSW) resource.
 49    $ref: /schemas/types.yaml#/definitions/phandle
 50
 51  regmap-mcba:
 52    description: Regmap of the MCB-A (memory bridge) resource.
 53    $ref: /schemas/types.yaml#/definitions/phandle
 54
 55  regmap-mcbb:
 56    description: Regmap of the MCB-B (memory bridge) resource.
 57    $ref: /schemas/types.yaml#/definitions/phandle
 58
 59  regmap-efuse:
 60    description: Regmap of the PMD efuse resource.
 61    $ref: /schemas/types.yaml#/definitions/phandle
 62
 63  regmap-rb:
 64    description: Regmap of the register bus resource (optional for compatibility).
 65    $ref: /schemas/types.yaml#/definitions/phandle
 66
 67required:
 68  - compatible
 69  - regmap-csw
 70  - regmap-mcba
 71  - regmap-mcbb
 72  - regmap-efuse
 73  - reg
 74  - interrupts
 75
 76# Child-node bindings
 77patternProperties:
 78  '^edacmc@':
 79    description: Memory controller subnode
 80    type: object
 81    additionalProperties: false
 82
 83    properties:
 84      compatible:
 85        const: apm,xgene-edac-mc
 86
 87      reg:
 88        maxItems: 1
 89
 90      memory-controller:
 91        description: Instance number of the memory controller.
 92        $ref: /schemas/types.yaml#/definitions/uint32
 93        maximum: 3
 94
 95    required:
 96      - compatible
 97      - reg
 98      - memory-controller
 99
100  '^edacpmd@':
101    description: PMD subnode
102    type: object
103    additionalProperties: false
104
105    properties:
106      compatible:
107        const: apm,xgene-edac-pmd
108
109      reg:
110        maxItems: 1
111
112      pmd-controller:
113        description: Instance number of the PMD controller.
114        $ref: /schemas/types.yaml#/definitions/uint32
115        maximum: 3
116
117    required:
118      - compatible
119      - reg
120      - pmd-controller
121
122  '^edacl3@':
123    description: L3 subnode
124    type: object
125    additionalProperties: false
126
127    properties:
128      compatible:
129        enum:
130          - apm,xgene-edac-l3
131          - apm,xgene-edac-l3-v2
132
133      reg:
134        maxItems: 1
135
136    required:
137      - compatible
138      - reg
139
140  '^edacsoc@':
141    description: SoC subnode
142    type: object
143    additionalProperties: false
144
145    properties:
146      compatible:
147        enum:
148          - apm,xgene-edac-soc
149          - apm,xgene-edac-soc-v1
150
151      reg:
152        maxItems: 1
153
154    required:
155      - compatible
156      - reg
157
158additionalProperties: false
159
160examples:
161  - |
162    bus {
163        #address-cells = <2>;
164        #size-cells = <2>;
165
166        edac@78800000 {
167            compatible = "apm,xgene-edac";
168            reg = <0x0 0x78800000 0x0 0x100>;
169            #address-cells = <2>;
170            #size-cells = <2>;
171            ranges;
172            interrupts = <0x0 0x20 0x4>, <0x0 0x21 0x4>, <0x0 0x27 0x4>;
173
174            regmap-csw = <&csw>;
175            regmap-mcba = <&mcba>;
176            regmap-mcbb = <&mcbb>;
177            regmap-efuse = <&efuse>;
178            regmap-rb = <&rb>;
179
180            edacmc@7e800000 {
181                compatible = "apm,xgene-edac-mc";
182                reg = <0x0 0x7e800000 0x0 0x1000>;
183                memory-controller = <0>;
184            };
185
186            edacpmd@7c000000 {
187                compatible = "apm,xgene-edac-pmd";
188                reg = <0x0 0x7c000000 0x0 0x200000>;
189                pmd-controller = <0>;
190            };
191
192            edacl3@7e600000 {
193                compatible = "apm,xgene-edac-l3";
194                reg = <0x0 0x7e600000 0x0 0x1000>;
195            };
196
197            edacsoc@7e930000 {
198                compatible = "apm,xgene-edac-soc-v1";
199                reg = <0x0 0x7e930000 0x0 0x1000>;
200            };
201        };
202    };