microchip,zl30731.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Microchip Azurite DPLL device
  8
  9maintainers:
 10  - Ivan Vecera <ivecera@redhat.com>
 11
 12description:
 13  Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
 14  provides up to 5 independent DPLL channels, up to 10 differential or
 15  single-ended inputs and 10 differential or 20 single-ended outputs.
 16  These devices support both I2C and SPI interfaces.
 17
 18properties:
 19  compatible:
 20    enum:
 21      - microchip,zl30731
 22      - microchip,zl30732
 23      - microchip,zl30733
 24      - microchip,zl30734
 25      - microchip,zl30735
 26
 27  reg:
 28    maxItems: 1
 29
 30required:
 31  - compatible
 32  - reg
 33
 34allOf:
 35  - $ref: /schemas/dpll/dpll-device.yaml#
 36  - $ref: /schemas/spi/spi-peripheral-props.yaml#
 37
 38unevaluatedProperties: false
 39
 40examples:
 41  - |
 42    i2c {
 43      #address-cells = <1>;
 44      #size-cells = <0>;
 45
 46      dpll@70 {
 47        compatible = "microchip,zl30732";
 48        reg = <0x70>;
 49        dpll-types = "pps", "eec";
 50
 51        input-pins {
 52          #address-cells = <1>;
 53          #size-cells = <0>;
 54
 55          pin@0 { /* REF0P */
 56            reg = <0>;
 57            connection-type = "ext";
 58            label = "Input 0";
 59            supported-frequencies-hz = /bits/ 64 <1 1000>;
 60          };
 61        };
 62
 63        output-pins {
 64          #address-cells = <1>;
 65          #size-cells = <0>;
 66
 67          pin@3 { /* OUT1N */
 68            reg = <3>;
 69            connection-type = "gnss";
 70            esync-control;
 71            label = "Output 1";
 72            supported-frequencies-hz = /bits/ 64 <1 10000>;
 73          };
 74        };
 75      };
 76    };
 77  - |
 78    spi {
 79      #address-cells = <1>;
 80      #size-cells = <0>;
 81
 82      dpll@70 {
 83        compatible = "microchip,zl30731";
 84        reg = <0x70>;
 85        spi-max-frequency = <12500000>;
 86
 87        dpll-types = "pps";
 88
 89        input-pins {
 90          #address-cells = <1>;
 91          #size-cells = <0>;
 92
 93          pin@0 { /* REF0P */
 94            reg = <0>;
 95            connection-type = "ext";
 96            label = "Input 0";
 97            supported-frequencies-hz = /bits/ 64 <1 1000>;
 98          };
 99        };
100
101        output-pins {
102          #address-cells = <1>;
103          #size-cells = <0>;
104
105          pin@3 { /* OUT1N */
106            reg = <3>;
107            connection-type = "gnss";
108            esync-control;
109            label = "Output 1";
110            supported-frequencies-hz = /bits/ 64 <1 10000>;
111          };
112        };
113      };
114    };
115...