k3-udma.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2# Copyright (C) 2019 Texas Instruments Incorporated
  3# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  4%YAML 1.2
  5---
  6$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
  7$schema: http://devicetree.org/meta-schemas/core.yaml#
  8
  9title: Texas Instruments K3 NAVSS Unified DMA
 10
 11maintainers:
 12  - Peter Ujfalusi <peter.ujfalusi@gmail.com>
 13
 14description: |
 15  The UDMA-P is intended to perform similar (but significantly upgraded)
 16  functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
 17  module supports the transmission and reception of various packet types.
 18  The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
 19  data structure compliant packets to/from smaller data blocks that are natively
 20  compatible with the specific requirements of each connected peripheral.
 21  Multiple Tx and Rx channels are provided within the DMA which allow multiple
 22  segmentation or reassembly operations to be ongoing. The DMA controller
 23  maintains state information for each of the channels which allows packet
 24  segmentation and reassembly operations to be time division multiplexed between
 25  channels in order to share the underlying DMA hardware. An external DMA
 26  scheduler is used to control the ordering and rate at which this multiplexing
 27  occurs for Transmit operations. The ordering and rate of Receive operations
 28  is indirectly controlled by the order in which blocks are pushed into the DMA
 29  on the Rx PSI-L interface.
 30
 31  The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
 32  channels. Channels in the UDMA-P can be configured to be either Packet-Based
 33  or Third-Party channels on a channel by channel basis.
 34
 35  All transfers within NAVSS is done between PSI-L source and destination
 36  threads.
 37  The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
 38  legacy, non PSI-L native peripherals. In the later case a special, small PDMA
 39  is tasked to act as a bridge between the PSI-L fabric and the legacy
 40  peripheral.
 41
 42  PDMAs can be configured via UDMAP peer registers to match with the
 43  configuration of the legacy peripheral.
 44
 45allOf:
 46  - $ref: ../dma-controller.yaml#
 47  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
 48
 49properties:
 50  "#dma-cells":
 51    minimum: 1
 52    maximum: 2
 53    description: |
 54      The cell is the PSI-L  thread ID of the remote (to UDMAP) end.
 55      Valid ranges for thread ID depends on the data movement direction:
 56      for source thread IDs (rx): 0 - 0x7fff
 57      for destination thread IDs (tx): 0x8000 - 0xffff
 58
 59      Please refer to the device documentation for the PSI-L thread map and also
 60      the PSI-L peripheral chapter for the correct thread ID.
 61
 62      When #dma-cells is 2, the second parameter is the channel ATYPE.
 63
 64  compatible:
 65    enum:
 66      - ti,am654-navss-main-udmap
 67      - ti,am654-navss-mcu-udmap
 68      - ti,j721e-navss-main-udmap
 69      - ti,j721e-navss-mcu-udmap
 70
 71  reg:
 72    minItems: 3
 73    items:
 74      - description: UDMA-P Control /Status Registers region
 75      - description: RX Channel Realtime Registers region
 76      - description: TX Channel Realtime Registers region
 77      - description: TX Configuration Registers region
 78      - description: RX Configuration Registers region
 79      - description: RX Flow Configuration Registers region
 80
 81  reg-names:
 82    minItems: 3
 83    items:
 84      - const: gcfg
 85      - const: rchanrt
 86      - const: tchanrt
 87      - const: tchan
 88      - const: rchan
 89      - const: rflow
 90
 91  msi-parent: true
 92
 93  ti,ringacc:
 94    description: phandle to the ring accelerator node
 95    $ref: /schemas/types.yaml#/definitions/phandle
 96
 97  ti,sci-rm-range-tchan:
 98    description: |
 99      Array of UDMA tchan resource subtypes for resource allocation for this
100      host
101    $ref: /schemas/types.yaml#/definitions/uint32-array
102    minItems: 1
103    # Should be enough
104    maxItems: 255
105
106  ti,sci-rm-range-rchan:
107    description: |
108      Array of UDMA rchan resource subtypes for resource allocation for this
109      host
110    $ref: /schemas/types.yaml#/definitions/uint32-array
111    minItems: 1
112    # Should be enough
113    maxItems: 255
114
115  ti,sci-rm-range-rflow:
116    description: |
117      Array of UDMA rflow resource subtypes for resource allocation for this
118      host
119    $ref: /schemas/types.yaml#/definitions/uint32-array
120    minItems: 1
121    # Should be enough
122    maxItems: 255
123
124required:
125  - compatible
126  - "#dma-cells"
127  - reg
128  - reg-names
129  - msi-parent
130  - ti,sci
131  - ti,sci-dev-id
132  - ti,ringacc
133  - ti,sci-rm-range-tchan
134  - ti,sci-rm-range-rchan
135  - ti,sci-rm-range-rflow
136
137if:
138  properties:
139    "#dma-cells":
140      const: 2
141then:
142  properties:
143    ti,udma-atype:
144      description: ATYPE value which should be used by non slave channels
145      $ref: /schemas/types.yaml#/definitions/uint32
146
147  required:
148    - ti,udma-atype
149
150unevaluatedProperties: false
151
152examples:
153  - |+
154    cbass_main {
155        #address-cells = <2>;
156        #size-cells = <2>;
157
158        cbass_main_navss: navss@30800000 {
159            compatible = "simple-mfd";
160            #address-cells = <2>;
161            #size-cells = <2>;
162            dma-coherent;
163            dma-ranges;
164            ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
165
166            ti,sci-dev-id = <118>;
167
168            main_udmap: dma-controller@31150000 {
169                compatible = "ti,am654-navss-main-udmap";
170                reg = <0x0 0x31150000 0x0 0x100>,
171                      <0x0 0x34000000 0x0 0x100000>,
172                      <0x0 0x35000000 0x0 0x100000>,
173                      <0x0 0x30b00000 0x0 0x20000>,
174                      <0x0 0x30c00000 0x0 0x8000>,
175                      <0x0 0x30d00000 0x0 0x4000>;
176                reg-names = "gcfg", "rchanrt", "tchanrt", "tchan", "rchan", "rflow";
177                #dma-cells = <1>;
178
179                ti,ringacc = <&ringacc>;
180
181                msi-parent = <&inta_main_udmass>;
182
183                ti,sci = <&dmsc>;
184                ti,sci-dev-id = <188>;
185
186                ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
187                                        <0x2>; /* TX_CHAN */
188                ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
189                                        <0x5>; /* RX_CHAN */
190                ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
191            };
192        };
193    };