st,stm32-mdma.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: STMicroelectronics STM32 MDMA Controller
  8
  9description: |
 10  The STM32 MDMA is a general-purpose direct memory access controller capable of
 11  supporting 64 independent DMA channels with 256 HW requests.
 12  DMA clients connected to the STM32 MDMA controller must use the format
 13  described in the dma.txt file, using a five-cell specifier for each channel:
 14  a phandle to the MDMA controller plus the following five integer cells:
 15    1. The request line number
 16    2. The priority level
 17      0x0: Low
 18      0x1: Medium
 19      0x2: High
 20      0x3: Very high
 21    3. A 32bit mask specifying the DMA channel configuration
 22      -bit 0-1: Source increment mode
 23        0x0: Source address pointer is fixed
 24        0x2: Source address pointer is incremented after each data transfer
 25        0x3: Source address pointer is decremented after each data transfer
 26      -bit 2-3: Destination increment mode
 27        0x0: Destination address pointer is fixed
 28        0x2: Destination address pointer is incremented after each data transfer
 29        0x3: Destination address pointer is decremented after each data transfer
 30      -bit 8-9: Source increment offset size
 31        0x0: byte (8bit)
 32        0x1: half-word (16bit)
 33        0x2: word (32bit)
 34        0x3: double-word (64bit)
 35      -bit 10-11: Destination increment offset size
 36        0x0: byte (8bit)
 37        0x1: half-word (16bit)
 38        0x2: word (32bit)
 39        0x3: double-word (64bit)
 40      -bit 25-18: The number of bytes to be transferred in a single transfer
 41                  (min = 1 byte, max = 128 bytes)
 42      -bit 29:28: Trigger Mode
 43        0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
 44        0x1: Each MDMA request triggers a block transfer (max 64K bytes)
 45        0x2: Each MDMA request triggers a repeated block transfer
 46        0x3: Each MDMA request triggers a linked list transfer
 47    4. A 32bit value specifying the register to be used to acknowledge the request
 48       if no HW ack signal is used by the MDMA client
 49    5. A 32bit mask specifying the value to be written to acknowledge the request
 50       if no HW ack signal is used by the MDMA client
 51
 52maintainers:
 53  - Amelie Delaunay <amelie.delaunay@foss.st.com>
 54
 55allOf:
 56  - $ref: /schemas/dma/dma-controller.yaml#
 57
 58properties:
 59  "#dma-cells":
 60    const: 5
 61
 62  compatible:
 63    const: st,stm32h7-mdma
 64
 65  reg:
 66    maxItems: 1
 67
 68  clocks:
 69    maxItems: 1
 70
 71  interrupts:
 72    maxItems: 1
 73
 74  resets:
 75    maxItems: 1
 76
 77  st,ahb-addr-masks:
 78    $ref: /schemas/types.yaml#/definitions/uint32-array
 79    description: Array of u32 mask to list memory devices addressed via AHB bus.
 80
 81required:
 82  - compatible
 83  - reg
 84  - clocks
 85  - interrupts
 86
 87unevaluatedProperties: false
 88
 89examples:
 90  - |
 91    #include <dt-bindings/interrupt-controller/arm-gic.h>
 92    #include <dt-bindings/clock/stm32mp1-clks.h>
 93    #include <dt-bindings/reset/stm32mp1-resets.h>
 94    dma-controller@52000000 {
 95      compatible = "st,stm32h7-mdma";
 96      reg = <0x52000000 0x1000>;
 97      interrupts = <122>;
 98      clocks = <&timer_clk>;
 99      resets = <&rcc 992>;
100      #dma-cells = <5>;
101      dma-channels = <16>;
102      dma-requests = <32>;
103      st,ahb-addr-masks = <0x20000000>, <0x00000000>;
104    };
105
106...