st,stm32-dma3.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: STMicroelectronics STM32 DMA3 Controller
  8
  9description: |
 10  The STM32 DMA3 is a direct memory access controller with different features
 11  depending on its hardware configuration.
 12  It is either called LPDMA (Low Power), GPDMA (General Purpose) or HPDMA (High
 13  Performance).
 14  Its hardware configuration registers allow to dynamically expose its features.
 15
 16  GPDMA and HPDMA support 16 independent DMA channels, while only 4 for LPDMA.
 17  GPDMA and HPDMA support 256 DMA requests from peripherals, 8 for LPDMA.
 18
 19  Bindings are generic for these 3 STM32 DMA3 configurations.
 20
 21  DMA clients connected to the STM32 DMA3 controller must use the format
 22  described in "#dma-cells" property description below, using a three-cell
 23  specifier for each channel.
 24
 25maintainers:
 26  - Amelie Delaunay <amelie.delaunay@foss.st.com>
 27
 28allOf:
 29  - $ref: /schemas/dma/dma-controller.yaml#
 30
 31properties:
 32  compatible:
 33    const: st,stm32mp25-dma3
 34
 35  reg:
 36    maxItems: 1
 37
 38  interrupts:
 39    minItems: 4
 40    maxItems: 16
 41    description:
 42      Should contain all of the per-channel DMA interrupts in ascending order
 43      with respect to the DMA channel index.
 44
 45  clocks:
 46    maxItems: 1
 47
 48  resets:
 49    maxItems: 1
 50
 51  power-domains:
 52    maxItems: 1
 53
 54  "#dma-cells":
 55    const: 3
 56    description: |
 57      Specifies the number of cells needed to provide DMA controller specific
 58      information.
 59      The first cell is the request line number.
 60      The second cell is a 32-bit mask specifying the DMA channel requirements:
 61        -bit 0-1: The priority level
 62          0x0: low priority, low weight
 63          0x1: low priority, mid weight
 64          0x2: low priority, high weight
 65          0x3: high priority
 66        -bit 4-7: The FIFO requirement for queuing source/destination transfers
 67          0x0: no FIFO requirement/any channel can fit
 68          0x2: FIFO of 8 bytes (2^2+1)
 69          0x4: FIFO of 32 bytes (2^4+1)
 70          0x6: FIFO of 128 bytes (2^6+1)
 71          0x7: FIFO of 256 bytes (2^7+1)
 72      The third cell is a 32-bit mask specifying the DMA transfer requirements:
 73        -bit 0: The source incrementing burst
 74          0x0: fixed burst
 75          0x1: contiguously incremented burst
 76        -bit 1: The source allocated port
 77          0x0: port 0 is allocated to the source transfer
 78          0x1: port 1 is allocated to the source transfer
 79        -bit 4: The destination incrementing burst
 80          0x0: fixed burst
 81          0x1: contiguously incremented burst
 82        -bit 5: The destination allocated port
 83          0x0: port 0 is allocated to the destination transfer
 84          0x1: port 1 is allocated to the destination transfer
 85        -bit 8: The type of hardware request
 86          0x0: burst
 87          0x1: block
 88        -bit 9: The control mode
 89          0x0: DMA controller control mode
 90          0x1: peripheral control mode
 91        -bit 12-13: The transfer complete event mode
 92          0x0: at block level, transfer complete event is generated at the end
 93               of a block
 94          0x2: at LLI level, the transfer complete event is generated at the end
 95               of the LLI transfer
 96               including the update of the LLI if any
 97          0x3: at channel level, the transfer complete event is generated at the
 98               end of the last LLI
 99        -bit 16: Prevent packing/unpacking mode
100          0x0: pack/unpack enabled when source data width/burst != destination data width/burst
101          0x1: memory data width/burst forced to peripheral data width/burst to prevent pack/unpack
102        -bit 17: Prevent additional transfers due to linked-list refactoring
103          0x0: don't prevent additional transfers for optimal performance
104          0x1: prevent additional transfer to accommodate user constraints such as single transfer
105
106required:
107  - compatible
108  - reg
109  - interrupts
110  - clocks
111  - "#dma-cells"
112
113unevaluatedProperties: false
114
115examples:
116  - |
117    #include <dt-bindings/interrupt-controller/arm-gic.h>
118    #include <dt-bindings/clock/st,stm32mp25-rcc.h>
119    dma-controller@40400000 {
120      compatible = "st,stm32mp25-dma3";
121      reg = <0x40400000 0x1000>;
122      interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
123                   <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
124                   <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
125                   <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
126                   <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
127                   <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
128                   <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
129                   <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
130                   <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
131                   <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
132                   <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
133                   <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
134                   <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
135                   <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
136                   <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
137                   <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
138      clocks = <&rcc CK_BUS_HPDMA1>;
139      #dma-cells = <3>;
140    };
141...