st,stm32-dma.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: STMicroelectronics STM32 DMA Controller
  8
  9description: |
 10  The STM32 DMA is a general-purpose direct memory access controller capable of
 11  supporting 8 independent DMA channels. Each channel can have up to 8 requests.
 12  DMA clients connected to the STM32 DMA controller must use the format
 13  described in the dma.txt file, using a four-cell specifier for each
 14  channel: a phandle to the DMA controller plus the following four integer cells:
 15    1. The channel id
 16    2. The request line number
 17    3. A 32bit mask specifying the DMA channel configuration which are device
 18      dependent:
 19        -bit 9: Peripheral Increment Address
 20          0x0: no address increment between transfers
 21          0x1: increment address between transfers
 22        -bit 10: Memory Increment Address
 23          0x0: no address increment between transfers
 24          0x1: increment address between transfers
 25        -bit 15: Peripheral Increment Offset Size
 26          0x0: offset size is linked to the peripheral bus width
 27          0x1: offset size is fixed to 4 (32-bit alignment)
 28        -bit 16-17: Priority level
 29          0x0: low
 30          0x1: medium
 31          0x2: high
 32          0x3: very high
 33    4. A 32bit bitfield value specifying DMA features which are device dependent:
 34       -bit 0-1: DMA FIFO threshold selection
 35         0x0: 1/4 full FIFO
 36         0x1: 1/2 full FIFO
 37         0x2: 3/4 full FIFO
 38         0x3: full FIFO
 39       -bit 2: DMA direct mode
 40         0x0: FIFO mode with threshold selectable with bit 0-1
 41         0x1: Direct mode: each DMA request immediately initiates a transfer
 42              from/to the memory, FIFO is bypassed.
 43       -bit 4: alternative DMA request/acknowledge protocol
 44         0x0: Use standard DMA ACK management, where ACK signal is maintained
 45              up to the removal of request and transfer completion
 46         0x1: Use alternative DMA ACK management, where ACK de-assertion does
 47              not wait for the de-assertion of the REQuest, ACK is only managed
 48              by transfer completion. This must only be used on channels
 49              managing transfers for STM32 USART/UART.
 50
 51maintainers:
 52  - Amelie Delaunay <amelie.delaunay@foss.st.com>
 53
 54allOf:
 55  - $ref: /schemas/dma/dma-controller.yaml#
 56
 57properties:
 58  "#dma-cells":
 59    const: 4
 60
 61  compatible:
 62    const: st,stm32-dma
 63
 64  reg:
 65    maxItems: 1
 66
 67  clocks:
 68    maxItems: 1
 69
 70  interrupts:
 71    maxItems: 8
 72    description: Should contain all of the per-channel DMA
 73      interrupts in ascending order with respect to the
 74      DMA channel index.
 75
 76  resets:
 77    maxItems: 1
 78
 79  st,mem2mem:
 80    $ref: /schemas/types.yaml#/definitions/flag
 81    description: if defined, it indicates that the controller
 82      supports memory-to-memory transfer
 83
 84  access-controllers:
 85    minItems: 1
 86    maxItems: 2
 87
 88required:
 89  - compatible
 90  - reg
 91  - clocks
 92  - interrupts
 93
 94unevaluatedProperties: false
 95
 96examples:
 97  - |
 98    #include <dt-bindings/interrupt-controller/arm-gic.h>
 99    #include <dt-bindings/clock/stm32mp1-clks.h>
100    #include <dt-bindings/reset/stm32mp1-resets.h>
101    dma-controller@40026400 {
102      compatible = "st,stm32-dma";
103      reg = <0x40026400 0x400>;
104      interrupts = <56>,
105                   <57>,
106                   <58>,
107                   <59>,
108                   <60>,
109                   <68>,
110                   <69>,
111                   <70>;
112      clocks = <&clk_hclk>;
113      #dma-cells = <4>;
114      st,mem2mem;
115      resets = <&rcc 150>;
116      dma-requests = <8>;
117    };
118
119...