snps,dw-axi-dmac.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Synopsys DesignWare AXI DMA Controller
  8
  9maintainers:
 10  - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 11
 12description:
 13  Synopsys DesignWare AXI DMA Controller DT Binding
 14
 15allOf:
 16  - $ref: dma-controller.yaml#
 17
 18properties:
 19  compatible:
 20    enum:
 21      - snps,axi-dma-1.01a
 22      - intel,kmb-axi-dma
 23      - starfive,jh7110-axi-dma
 24      - starfive,jh8100-axi-dma
 25
 26  reg:
 27    minItems: 1
 28    items:
 29      - description: Address range of the DMAC registers
 30      - description: Address range of the DMAC APB registers
 31
 32  reg-names:
 33    items:
 34      - const: axidma_ctrl_regs
 35      - const: axidma_apb_regs
 36
 37  interrupts:
 38    description:
 39      If the IP-core synthesis parameter DMAX_INTR_IO_TYPE is set to 1, this
 40      will be per-channel interrupts. Otherwise, this is a single combined IRQ
 41      for all channels.
 42    minItems: 1
 43    maxItems: 8
 44
 45  iommus:
 46    maxItems: 1
 47
 48  clocks:
 49    items:
 50      - description: Bus Clock
 51      - description: Module Clock
 52
 53  clock-names:
 54    items:
 55      - const: core-clk
 56      - const: cfgr-clk
 57
 58  '#dma-cells':
 59    const: 1
 60
 61  dma-channels:
 62    minimum: 1
 63    maximum: 8
 64
 65  dma-noncoherent: true
 66
 67  resets:
 68    minItems: 1
 69    maxItems: 2
 70
 71  snps,dma-masters:
 72    description: |
 73      Number of AXI masters supported by the hardware.
 74    $ref: /schemas/types.yaml#/definitions/uint32
 75    enum: [1, 2]
 76
 77  snps,data-width:
 78    description: |
 79      AXI data width supported by hardware.
 80      (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
 81    $ref: /schemas/types.yaml#/definitions/uint32
 82    enum: [0, 1, 2, 3, 4, 5, 6]
 83
 84  snps,priority:
 85    description: |
 86      Channel priority specifier associated with the DMA channels.
 87    $ref: /schemas/types.yaml#/definitions/uint32-array
 88    minItems: 1
 89    maxItems: 8
 90
 91  snps,block-size:
 92    description: |
 93      Channel block size specifier associated with the DMA channels.
 94    $ref: /schemas/types.yaml#/definitions/uint32-array
 95    minItems: 1
 96    maxItems: 8
 97
 98  snps,axi-max-burst-len:
 99    description: |
100      Restrict master AXI burst length by value specified in this property.
101      If this property is missing the maximum AXI burst length supported by
102      DMAC is used.
103    $ref: /schemas/types.yaml#/definitions/uint32
104    minimum: 1
105    maximum: 256
106
107required:
108  - compatible
109  - reg
110  - clocks
111  - clock-names
112  - interrupts
113  - '#dma-cells'
114  - dma-channels
115  - snps,dma-masters
116  - snps,data-width
117  - snps,priority
118  - snps,block-size
119
120if:
121  properties:
122    compatible:
123      contains:
124        enum:
125          - starfive,jh7110-axi-dma
126then:
127  properties:
128    resets:
129      minItems: 2
130      items:
131        - description: AXI reset line
132        - description: AHB reset line
133        - description: module reset
134else:
135  properties:
136    resets:
137      maxItems: 1
138
139additionalProperties: false
140
141examples:
142  - |
143    #include <dt-bindings/interrupt-controller/arm-gic.h>
144    #include <dt-bindings/interrupt-controller/irq.h>
145    /* example with snps,dw-axi-dmac */
146    dma-controller@80000 {
147        compatible = "snps,axi-dma-1.01a";
148        reg = <0x80000 0x400>;
149        clocks = <&core_clk>, <&cfgr_clk>;
150        clock-names = "core-clk", "cfgr-clk";
151        interrupt-parent = <&intc>;
152        interrupts = <27>;
153        #dma-cells = <1>;
154        dma-channels = <4>;
155        snps,dma-masters = <2>;
156        snps,data-width = <3>;
157        snps,block-size = <4096 4096 4096 4096>;
158        snps,priority = <0 1 2 3>;
159        snps,axi-max-burst-len = <16>;
160    };