renesas,rz-dmac.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Renesas RZ DMA Controller
  8
  9maintainers:
 10  - Biju Das <biju.das.jz@bp.renesas.com>
 11
 12properties:
 13  compatible:
 14    oneOf:
 15      - items:
 16          - enum:
 17              - renesas,r7s72100-dmac # RZ/A1H
 18              - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
 19              - renesas,r9a07g044-dmac # RZ/G2{L,LC}
 20              - renesas,r9a07g054-dmac # RZ/V2L
 21              - renesas,r9a08g045-dmac # RZ/G3S
 22          - const: renesas,rz-dmac
 23
 24      - items:
 25          - enum:
 26              - renesas,r9a09g047-dmac # RZ/G3E
 27          - const: renesas,r9a09g057-dmac
 28
 29      - const: renesas,r9a09g057-dmac # RZ/V2H(P)
 30
 31  reg:
 32    items:
 33      - description: Control and channel register block
 34      - description: DMA extended resource selector block
 35    minItems: 1
 36
 37  interrupts:
 38    maxItems: 17
 39
 40  interrupt-names:
 41    items:
 42      - const: error
 43      - const: ch0
 44      - const: ch1
 45      - const: ch2
 46      - const: ch3
 47      - const: ch4
 48      - const: ch5
 49      - const: ch6
 50      - const: ch7
 51      - const: ch8
 52      - const: ch9
 53      - const: ch10
 54      - const: ch11
 55      - const: ch12
 56      - const: ch13
 57      - const: ch14
 58      - const: ch15
 59
 60  clocks:
 61    items:
 62      - description: DMA main clock
 63      - description: DMA register access clock
 64    minItems: 1
 65
 66  clock-names:
 67    items:
 68      - const: main
 69      - const: register
 70
 71  '#dma-cells':
 72    const: 1
 73    description:
 74      The cell specifies the encoded MID/RID or the REQ No values of
 75      the DMAC port connected to the DMA client and the slave channel
 76      configuration parameters.
 77      bits[0:9] - Specifies the MID/RID or the REQ No value
 78      bit[10] - Specifies DMA request high enable (HIEN)
 79      bit[11] - Specifies DMA request detection type (LVL)
 80      bits[12:14] - Specifies DMAACK output mode (AM)
 81      bit[15] - Specifies Transfer Mode (TM)
 82
 83  dma-channels:
 84    const: 16
 85
 86  power-domains:
 87    maxItems: 1
 88
 89  resets:
 90    items:
 91      - description: Reset for DMA ARESETN reset terminal
 92      - description: Reset for DMA RST_ASYNC reset terminal
 93    minItems: 1
 94
 95  reset-names:
 96    items:
 97      - const: arst
 98      - const: rst_async
 99
100  renesas,icu:
101    description:
102      It must contain the phandle to the ICU and the index of the DMAC as seen
103      from the ICU.
104    $ref: /schemas/types.yaml#/definitions/phandle-array
105    items:
106      - items:
107          - description: Phandle to the ICU node.
108          - description:
109              The number of the DMAC as seen from the ICU, i.e. parameter k from
110              register ICU_DMkSELy. This may differ from the actual DMAC instance
111              number.
112
113required:
114  - compatible
115  - reg
116  - interrupts
117  - interrupt-names
118  - '#dma-cells'
119  - dma-channels
120
121allOf:
122  - $ref: dma-controller.yaml#
123
124  - if:
125      properties:
126        compatible:
127          contains:
128            enum:
129              - renesas,r9a07g043-dmac
130              - renesas,r9a07g044-dmac
131              - renesas,r9a07g054-dmac
132              - renesas,r9a08g045-dmac
133    then:
134      properties:
135        reg:
136          minItems: 2
137        clocks:
138          minItems: 2
139        resets:
140          minItems: 2
141
142        renesas,icu: false
143
144      required:
145        - clocks
146        - clock-names
147        - power-domains
148        - resets
149        - reset-names
150
151  - if:
152      properties:
153        compatible:
154          contains:
155            const: renesas,r7s72100-dmac
156    then:
157      properties:
158        reg:
159          minItems: 2
160
161        clocks: false
162        clock-names: false
163        power-domains: false
164        resets: false
165        reset-names: false
166        renesas,icu: false
167
168  - if:
169      properties:
170        compatible:
171          contains:
172            const: renesas,r9a09g057-dmac
173    then:
174      properties:
175        reg:
176          maxItems: 1
177        clocks:
178          maxItems: 1
179        resets:
180          maxItems: 1
181
182        clock-names: false
183        reset-names: false
184
185      required:
186        - clocks
187        - power-domains
188        - renesas,icu
189        - resets
190
191additionalProperties: false
192
193examples:
194  - |
195    #include <dt-bindings/interrupt-controller/arm-gic.h>
196    #include <dt-bindings/clock/r9a07g044-cpg.h>
197
198    dmac: dma-controller@11820000 {
199        compatible = "renesas,r9a07g044-dmac",
200                     "renesas,rz-dmac";
201        reg = <0x11820000 0x10000>,
202              <0x11830000 0x10000>;
203        interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
204                     <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
205                     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
206                     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
207                     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
208                     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
209                     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
210                     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
211                     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
212                     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
213                     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
214                     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
215                     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
216                     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
217                     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
218                     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
219                     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
220        interrupt-names = "error",
221                          "ch0", "ch1", "ch2", "ch3",
222                          "ch4", "ch5", "ch6", "ch7",
223                          "ch8", "ch9", "ch10", "ch11",
224                          "ch12", "ch13", "ch14", "ch15";
225        clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
226                 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
227        clock-names = "main", "register";
228        power-domains = <&cpg>;
229        resets = <&cpg R9A07G044_DMAC_ARESETN>,
230                 <&cpg R9A07G044_DMAC_RST_ASYNC>;
231        reset-names = "arst", "rst_async";
232        #dma-cells = <1>;
233        dma-channels = <16>;
234    };