qcom,gpi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Technologies Inc GPI DMA controller
  8
  9maintainers:
 10  - Vinod Koul <vkoul@kernel.org>
 11
 12description: |
 13  QCOM GPI DMA controller provides DMA capabilities for
 14  peripheral buses such as I2C, UART, and SPI.
 15
 16allOf:
 17  - $ref: dma-controller.yaml#
 18
 19properties:
 20  compatible:
 21    oneOf:
 22      - enum:
 23          - qcom,sdm845-gpi-dma
 24          - qcom,sm6350-gpi-dma
 25      - items:
 26          - enum:
 27              - qcom,milos-gpi-dma
 28              - qcom,qcm2290-gpi-dma
 29              - qcom,qcs8300-gpi-dma
 30              - qcom,qdu1000-gpi-dma
 31              - qcom,sa8775p-gpi-dma
 32              - qcom,sar2130p-gpi-dma
 33              - qcom,sc7280-gpi-dma
 34              - qcom,sc8280xp-gpi-dma
 35              - qcom,sdx75-gpi-dma
 36              - qcom,sm6115-gpi-dma
 37              - qcom,sm6375-gpi-dma
 38              - qcom,sm8350-gpi-dma
 39              - qcom,sm8450-gpi-dma
 40              - qcom,sm8550-gpi-dma
 41              - qcom,sm8650-gpi-dma
 42              - qcom,sm8750-gpi-dma
 43              - qcom,x1e80100-gpi-dma
 44          - const: qcom,sm6350-gpi-dma
 45      - items:
 46          - enum:
 47              - qcom,qcs615-gpi-dma
 48              - qcom,sdm670-gpi-dma
 49              - qcom,sm6125-gpi-dma
 50              - qcom,sm8150-gpi-dma
 51              - qcom,sm8250-gpi-dma
 52          - const: qcom,sdm845-gpi-dma
 53
 54  reg:
 55    maxItems: 1
 56
 57  interrupts:
 58    description:
 59      Interrupt lines for each GPI instance
 60    minItems: 1
 61    maxItems: 13
 62
 63  "#dma-cells":
 64    const: 3
 65    description: >
 66      DMA clients must use the format described in dma.txt, giving a phandle
 67      to the DMA controller plus the following 3 integer cells:
 68      - channel: if set to 0xffffffff, any available channel will be allocated
 69        for the client. Otherwise, the exact channel specified will be used.
 70      - seid: serial id of the client as defined in the SoC documentation.
 71      - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
 72
 73  iommus:
 74    maxItems: 1
 75
 76  dma-channels:
 77    maximum: 31
 78
 79  dma-channel-mask:
 80    maxItems: 1
 81
 82  dma-coherent: true
 83
 84required:
 85  - compatible
 86  - reg
 87  - interrupts
 88  - "#dma-cells"
 89  - iommus
 90  - dma-channels
 91  - dma-channel-mask
 92
 93additionalProperties: false
 94
 95examples:
 96  - |
 97    #include <dt-bindings/interrupt-controller/arm-gic.h>
 98    #include <dt-bindings/dma/qcom-gpi.h>
 99    gpi_dma0: dma-controller@800000 {
100        compatible = "qcom,sdm845-gpi-dma";
101        #dma-cells = <3>;
102        reg = <0x00800000 0x60000>;
103        iommus = <&apps_smmu 0x0016 0x0>;
104        dma-channels = <13>;
105        dma-channel-mask = <0xfa>;
106        interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
107                     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
108                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
109                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
110                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
111                     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
112                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
113                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
114                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
115                     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
116                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
117                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
118                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
119    };
120
121...