nvidia,tegra20-apbdma.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/dma/nvidia,tegra20-apbdma.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NVIDIA Tegra APB DMA Controller
  8
  9description:
 10  The NVIDIA Tegra APB DMA controller is a hardware component that
 11  enables direct memory access (DMA) on Tegra systems. It facilitates
 12  data transfer between I/O devices and main memory without constant
 13  CPU intervention.
 14
 15maintainers:
 16  - Jonathan Hunter <jonathanh@nvidia.com>
 17
 18properties:
 19  compatible:
 20    oneOf:
 21      - enum:
 22          - nvidia,tegra114-apbdma
 23          - nvidia,tegra20-apbdma
 24      - items:
 25          - const: nvidia,tegra30-apbdma
 26          - const: nvidia,tegra20-apbdma
 27      - items:
 28          - enum:
 29              - nvidia,tegra124-apbdma
 30              - nvidia,tegra210-apbdma
 31          - const: nvidia,tegra148-apbdma
 32
 33  reg:
 34    maxItems: 1
 35
 36  "#dma-cells":
 37    const: 1
 38
 39  clocks:
 40    maxItems: 1
 41
 42  clock-names:
 43    const: dma
 44
 45  interrupts:
 46    description:
 47      Should contain all of the per-channel DMA interrupts in
 48      ascending order with respect to the DMA channel index.
 49    minItems: 1
 50    maxItems: 32
 51
 52  resets:
 53    maxItems: 1
 54
 55  reset-names:
 56    const: dma
 57
 58required:
 59  - compatible
 60  - reg
 61  - "#dma-cells"
 62  - clocks
 63  - interrupts
 64  - resets
 65  - reset-names
 66
 67allOf:
 68  - $ref: dma-controller.yaml#
 69
 70unevaluatedProperties: false
 71
 72examples:
 73  - |
 74    #include <dt-bindings/interrupt-controller/arm-gic.h>
 75    #include <dt-bindings/reset/tegra186-reset.h>
 76    dma-controller@6000a000 {
 77        compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 78        reg = <0x6000a000 0x1200>;
 79        interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 80                     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 81                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 82                     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 83                     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 84                     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 85                     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 86                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 87                     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 88                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 89                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 90                     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 91                     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 92                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 93                     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 94                     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 95        clocks = <&tegra_car 34>;
 96        resets = <&tegra_car 34>;
 97        reset-names = "dma";
 98        #dma-cells = <1>;
 99    };
100...