nvidia,tegra186-gpc-dma.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NVIDIA Tegra GPC DMA Controller
  8
  9description: |
 10  The Tegra General Purpose Central (GPC) DMA controller is used for faster
 11  data transfers between memory to memory, memory to device and device to
 12  memory.
 13
 14maintainers:
 15  - Jon Hunter <jonathanh@nvidia.com>
 16  - Rajesh Gumasta <rgumasta@nvidia.com>
 17
 18allOf:
 19  - $ref: dma-controller.yaml#
 20
 21properties:
 22  compatible:
 23    oneOf:
 24      - const: nvidia,tegra186-gpcdma
 25      - items:
 26          - enum:
 27              - nvidia,tegra264-gpcdma
 28              - nvidia,tegra234-gpcdma
 29              - nvidia,tegra194-gpcdma
 30          - const: nvidia,tegra186-gpcdma
 31
 32  "#dma-cells":
 33    const: 1
 34
 35  reg:
 36    maxItems: 1
 37
 38  interrupts:
 39    description:
 40      Should contain all of the per-channel DMA interrupts in
 41      ascending order with respect to the DMA channel index.
 42    minItems: 1
 43    maxItems: 32
 44
 45  resets:
 46    maxItems: 1
 47
 48  reset-names:
 49    const: gpcdma
 50
 51  iommus:
 52    maxItems: 1
 53
 54  dma-coherent: true
 55
 56  dma-channel-mask:
 57    maxItems: 1
 58
 59required:
 60  - compatible
 61  - reg
 62  - interrupts
 63  - resets
 64  - reset-names
 65  - "#dma-cells"
 66  - iommus
 67  - dma-channel-mask
 68
 69additionalProperties: false
 70
 71examples:
 72  - |
 73    #include <dt-bindings/interrupt-controller/arm-gic.h>
 74    #include <dt-bindings/memory/tegra186-mc.h>
 75    #include <dt-bindings/reset/tegra186-reset.h>
 76
 77    dma-controller@2600000 {
 78        compatible = "nvidia,tegra186-gpcdma";
 79        reg = <0x2600000 0x210000>;
 80        resets = <&bpmp TEGRA186_RESET_GPCDMA>;
 81        reset-names = "gpcdma";
 82        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 83                     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 84                     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 85                     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 86                     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 87                     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
 88                     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
 89                     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
 90                     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 91                     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 92                     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 93                     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 94                     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 95                     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 96                     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 97                     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 98                     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 99                     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
100                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
101                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
102                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
103                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
104                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
105                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
106                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
107                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
108                     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
109                     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
110                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
111                     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
112                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
113        #dma-cells = <1>;
114        iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
115        dma-coherent;
116        dma-channel-mask = <0xfffffffe>;
117    };
118...