intel,ldma.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Lightning Mountain centralized DMA controllers.
  8
  9maintainers:
 10  - chuanhua.lei@intel.com
 11  - mallikarjunax.reddy@intel.com
 12
 13allOf:
 14  - $ref: dma-controller.yaml#
 15
 16properties:
 17  compatible:
 18    enum:
 19      - intel,lgm-cdma
 20      - intel,lgm-dma2tx
 21      - intel,lgm-dma1rx
 22      - intel,lgm-dma1tx
 23      - intel,lgm-dma0tx
 24      - intel,lgm-dma3
 25      - intel,lgm-toe-dma30
 26      - intel,lgm-toe-dma31
 27
 28  reg:
 29    maxItems: 1
 30
 31  "#dma-cells":
 32    const: 3
 33    description:
 34      The first cell is the peripheral's DMA request line.
 35      The second cell is the peripheral's (port) number corresponding to the channel.
 36      The third cell is the burst length of the channel.
 37
 38  dma-channels:
 39    minimum: 1
 40    maximum: 16
 41
 42  dma-channel-mask:
 43    maxItems: 1
 44
 45  clocks:
 46    maxItems: 1
 47
 48  resets:
 49    maxItems: 1
 50
 51  reset-names:
 52    items:
 53      - const: ctrl
 54
 55  interrupts:
 56    maxItems: 1
 57
 58  intel,dma-poll-cnt:
 59    $ref: /schemas/types.yaml#/definitions/uint32
 60    description:
 61      DMA descriptor polling counter is used to control the poling mechanism
 62      for the descriptor fetching for all channels.
 63
 64  intel,dma-byte-en:
 65    type: boolean
 66    description:
 67      DMA byte enable is only valid for DMA write(RX).
 68      Byte enable(1) means DMA write will be based on the number of dwords
 69      instead of the whole burst.
 70
 71  intel,dma-drb:
 72    type: boolean
 73    description:
 74      DMA descriptor read back to make sure data and desc synchronization.
 75
 76  intel,dma-dburst-wr:
 77    type: boolean
 78    description:
 79      Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst;
 80      if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16.
 81      It only applies to RX DMA and memcopy DMA.
 82
 83required:
 84  - compatible
 85  - reg
 86
 87additionalProperties: false
 88
 89examples:
 90  - |
 91    dma0: dma-controller@e0e00000 {
 92      compatible = "intel,lgm-cdma";
 93      reg = <0xe0e00000 0x1000>;
 94      #dma-cells = <3>;
 95      dma-channels = <16>;
 96      dma-channel-mask = <0xFFFF>;
 97      interrupt-parent = <&ioapic1>;
 98      interrupts = <82 1>;
 99      resets = <&rcu0 0x30 0>;
100      reset-names = "ctrl";
101      clocks = <&cgu0 80>;
102      intel,dma-poll-cnt = <4>;
103      intel,dma-byte-en;
104      intel,dma-drb;
105    };
106  - |
107    dma3: dma-controller@ec800000 {
108      compatible = "intel,lgm-dma3";
109      reg = <0xec800000 0x1000>;
110      clocks = <&cgu0 71>;
111      resets = <&rcu0 0x10 9>;
112      #dma-cells = <3>;
113      intel,dma-poll-cnt = <16>;
114      intel,dma-byte-en;
115      intel,dma-dburst-wr;
116    };