fsl,elo3-dma.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale Elo3 DMA Controller
  8
  9maintainers:
 10  - J. Neuschäfer <j.ne@posteo.net>
 11
 12description:
 13  DMA controller which has same function as EloPlus except that Elo3 has 8
 14  channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
 15  series chips, such as t1040, t4240, b4860.
 16
 17properties:
 18  compatible:
 19    const: fsl,elo3-dma
 20
 21  reg:
 22    items:
 23      - description:
 24          DMA General Status Registers starting from DGSR0, for channel 1~4
 25      - description:
 26          DMA General Status Registers starting from DGSR1, for channel 5~8
 27
 28  ranges: true
 29
 30  "#address-cells":
 31    const: 1
 32
 33  "#size-cells":
 34    const: 1
 35
 36  interrupts:
 37    maxItems: 1
 38
 39patternProperties:
 40  "^dma-channel@[0-9a-f]+$":
 41    type: object
 42    additionalProperties: false
 43
 44    properties:
 45      compatible:
 46        enum:
 47          # native DMA channel
 48          - fsl,eloplus-dma-channel
 49
 50          # audio DMA channel, see fsl,ssi.yaml
 51          - fsl,ssi-dma-channel
 52
 53      reg:
 54        maxItems: 1
 55
 56      interrupts:
 57        maxItems: 1
 58        description:
 59          Per-channel interrupt. Only necessary if no controller interrupt has
 60          been provided.
 61
 62additionalProperties: false
 63
 64examples:
 65  - |
 66    #include <dt-bindings/interrupt-controller/irq.h>
 67
 68    dma@100300 {
 69        compatible = "fsl,elo3-dma";
 70        reg = <0x100300 0x4>,
 71              <0x100600 0x4>;
 72        #address-cells = <1>;
 73        #size-cells = <1>;
 74        ranges = <0x0 0x100100 0x500>;
 75
 76        dma-channel@0 {
 77            compatible = "fsl,eloplus-dma-channel";
 78            reg = <0x0 0x80>;
 79            interrupts = <28 IRQ_TYPE_EDGE_FALLING 0 0>;
 80        };
 81
 82        dma-channel@80 {
 83            compatible = "fsl,eloplus-dma-channel";
 84            reg = <0x80 0x80>;
 85            interrupts = <29 IRQ_TYPE_EDGE_FALLING 0 0>;
 86        };
 87
 88        dma-channel@100 {
 89            compatible = "fsl,eloplus-dma-channel";
 90            reg = <0x100 0x80>;
 91            interrupts = <30 IRQ_TYPE_EDGE_FALLING 0 0>;
 92        };
 93
 94        dma-channel@180 {
 95            compatible = "fsl,eloplus-dma-channel";
 96            reg = <0x180 0x80>;
 97            interrupts = <31 IRQ_TYPE_EDGE_FALLING 0 0>;
 98        };
 99
100        dma-channel@300 {
101            compatible = "fsl,eloplus-dma-channel";
102            reg = <0x300 0x80>;
103            interrupts = <76 IRQ_TYPE_EDGE_FALLING 0 0>;
104        };
105
106        dma-channel@380 {
107            compatible = "fsl,eloplus-dma-channel";
108            reg = <0x380 0x80>;
109            interrupts = <77 IRQ_TYPE_EDGE_FALLING 0 0>;
110        };
111
112        dma-channel@400 {
113            compatible = "fsl,eloplus-dma-channel";
114            reg = <0x400 0x80>;
115            interrupts = <78 IRQ_TYPE_EDGE_FALLING 0 0>;
116        };
117
118        dma-channel@480 {
119            compatible = "fsl,eloplus-dma-channel";
120            reg = <0x480 0x80>;
121            interrupts = <79 IRQ_TYPE_EDGE_FALLING 0 0>;
122        };
123    };
124
125...