ti,am65x-dss.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2# Copyright 2019 Texas Instruments Incorporated
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: Texas Instruments AM65x Display Subsystem
  9
 10maintainers:
 11  - Jyri Sarha <jsarha@ti.com>
 12  - Tomi Valkeinen <tomi.valkeinen@ti.com>
 13
 14description: |
 15  The AM625 and AM65x TI Keystone Display SubSystem has two output
 16  ports and two video planes. In AM65x DSS, the first video port
 17  supports 1 OLDI TX and in AM625 DSS, the first video port output is
 18  internally routed to 2 OLDI TXes. The second video port supports DPI
 19  format. The first plane is full video plane with all features and the
 20  second is a "lite plane" without scaling support.
 21  The AM62L display subsystem has a single output port which supports DPI
 22  format but it only supports single video "lite plane" which does not support
 23  scaling. The output port is routed to SoC boundary via DPI interface and same
 24  DPI signals are also routed internally to DSI Tx controller present within the
 25  SoC. Due to clocking limitations only one of the interface i.e. either DSI or
 26  DPI can be used at once.
 27
 28properties:
 29  compatible:
 30    enum:
 31      - ti,am625-dss
 32      - ti,am62a7-dss
 33      - ti,am62l-dss
 34      - ti,am65x-dss
 35
 36  reg:
 37    description:
 38      Addresses to each DSS memory region described in the SoC's TRM.
 39    items:
 40      - description: common DSS register area
 41      - description: VIDL1 light video plane
 42      - description: VID video plane
 43      - description: OVR1 overlay manager for vp1
 44      - description: OVR2 overlay manager for vp2
 45      - description: VP1 video port 1
 46      - description: VP2 video port 2
 47      - description: common1 DSS register area
 48
 49  reg-names:
 50    items:
 51      - const: common
 52      - const: vidl1
 53      - const: vid
 54      - const: ovr1
 55      - const: ovr2
 56      - const: vp1
 57      - const: vp2
 58      - const: common1
 59
 60  clocks:
 61    items:
 62      - description: fck DSS functional clock
 63      - description: vp1 Video Port 1 pixel clock
 64      - description: vp2 Video Port 2 pixel clock
 65
 66  clock-names:
 67    items:
 68      - const: fck
 69      - const: vp1
 70      - const: vp2
 71
 72  assigned-clocks:
 73    minItems: 1
 74    maxItems: 3
 75
 76  assigned-clock-parents:
 77    minItems: 1
 78    maxItems: 3
 79
 80  interrupts:
 81    maxItems: 1
 82
 83  power-domains:
 84    maxItems: 1
 85    description: phandle to the associated power domain
 86
 87  dma-coherent: true
 88
 89  ports:
 90    $ref: /schemas/graph.yaml#/properties/ports
 91
 92    properties:
 93      port@0:
 94        $ref: /schemas/graph.yaml#/properties/port
 95        description:
 96          For AM65x DSS, the OLDI output port node from video port 1.
 97          For AM625 DSS, the internal DPI output port node from video
 98          port 1.
 99          For AM62A7 DSS, the port is tied off inside the SoC.
100          For AM62L DSS, the DSS DPI output port node from video port 1
101          or DSI Tx controller node connected to video port 1.
102        properties:
103          endpoint@0:
104            $ref: /schemas/graph.yaml#/properties/endpoint
105            description:
106              For AM625 DSS, VP Connection to OLDI0.
107              For AM65X DSS, OLDI output from the SoC.
108
109          endpoint@1:
110            $ref: /schemas/graph.yaml#/properties/endpoint
111            description:
112              For AM625 DSS, VP Connection to OLDI1.
113
114        anyOf:
115          - required:
116              - endpoint
117          - required:
118              - endpoint@0
119              - endpoint@1
120
121      port@1:
122        $ref: /schemas/graph.yaml#/properties/port
123        description:
124          The DSS DPI output port node from video port 2
125
126  ti,am65x-oldi-io-ctrl:
127    $ref: /schemas/types.yaml#/definitions/phandle
128    description:
129      phandle to syscon device node mapping OLDI IO_CTRL registers.
130      The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
131      following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
132      and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
133      interface to work.
134
135  max-memory-bandwidth:
136    $ref: /schemas/types.yaml#/definitions/uint32
137    description:
138      Input memory (from main memory to dispc) bandwidth limit in
139      bytes per second
140
141  oldi-transmitters:
142    description:
143      Child node under the DSS, to describe all the OLDI transmitters connected
144      to the DSS videoports.
145    type: object
146    additionalProperties: false
147
148    properties:
149      "#address-cells":
150        const: 1
151
152      "#size-cells":
153        const: 0
154
155    patternProperties:
156      '^oldi@[0-1]$':
157        $ref: ti,am625-oldi.yaml#
158        description: OLDI transmitters connected to the DSS VPs
159
160allOf:
161  - if:
162      properties:
163        compatible:
164          contains:
165            const: ti,am62a7-dss
166    then:
167      properties:
168        oldi-transmitters: false
169        ports:
170          properties:
171            port@0: false
172  - if:
173      properties:
174        compatible:
175          contains:
176            const: ti,am62l-dss
177    then:
178      properties:
179        ports:
180          properties:
181            port@1: false
182
183  - if:
184      properties:
185        compatible:
186          contains:
187            enum:
188              - ti,am62l-dss
189              - ti,am65x-dss
190    then:
191      properties:
192        oldi-transmitters: false
193        ports:
194          properties:
195            port@0:
196              properties:
197                endpoint@1: false
198
199required:
200  - compatible
201  - reg
202  - reg-names
203  - clocks
204  - clock-names
205  - interrupts
206  - ports
207
208additionalProperties: false
209
210examples:
211  - |
212    #include <dt-bindings/interrupt-controller/arm-gic.h>
213    #include <dt-bindings/interrupt-controller/irq.h>
214    #include <dt-bindings/soc/ti,sci_pm_domain.h>
215
216    dss: dss@4a00000 {
217        compatible = "ti,am65x-dss";
218        reg = <0x04a00000 0x1000>, /* common */
219              <0x04a02000 0x1000>, /* vidl1 */
220              <0x04a06000 0x1000>, /* vid */
221              <0x04a07000 0x1000>, /* ovr1 */
222              <0x04a08000 0x1000>, /* ovr2 */
223              <0x04a0a000 0x1000>, /* vp1 */
224              <0x04a0b000 0x1000>, /* vp2 */
225              <0x04a01000 0x1000>; /* common1 */
226        reg-names = "common", "vidl1", "vid",
227                "ovr1", "ovr2", "vp1", "vp2", "common1";
228        ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
229        power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
230        clocks =        <&k3_clks 67 1>,
231                        <&k3_clks 216 1>,
232                        <&k3_clks 67 2>;
233        clock-names = "fck", "vp1", "vp2";
234        interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
235        ports {
236            #address-cells = <1>;
237            #size-cells = <0>;
238            port@0 {
239                reg = <0>;
240                oldi_out0: endpoint {
241                    remote-endpoint = <&lcd_in0>;
242                };
243            };
244        };
245    };
246
247  - |
248    #include <dt-bindings/interrupt-controller/arm-gic.h>
249    #include <dt-bindings/interrupt-controller/irq.h>
250    #include <dt-bindings/soc/ti,sci_pm_domain.h>
251
252    bus {
253        #address-cells = <2>;
254        #size-cells = <2>;
255        dss1: dss@30200000 {
256            compatible = "ti,am625-dss";
257            reg = <0x00 0x30200000 0x00 0x1000>, /* common */
258                  <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
259                  <0x00 0x30206000 0x00 0x1000>, /* vid */
260                  <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
261                  <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
262                  <0x00 0x3020a000 0x00 0x1000>, /* vp1 */
263                  <0x00 0x3020b000 0x00 0x1000>, /* vp2 */
264                  <0x00 0x30201000 0x00 0x1000>; /* common1 */
265            reg-names = "common", "vidl1", "vid",
266                        "ovr1", "ovr2", "vp1", "vp2", "common1";
267            power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
268            clocks =        <&k3_clks 186 6>,
269                            <&vp1_clock>,
270                            <&k3_clks 186 2>;
271            clock-names = "fck", "vp1", "vp2";
272            interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
273            oldi-transmitters {
274                #address-cells = <1>;
275                #size-cells = <0>;
276                oldi0: oldi@0 {
277                    reg = <0>;
278                    clocks = <&k3_clks 186 0>;
279                    clock-names = "serial";
280                    ti,companion-oldi = <&oldi1>;
281                    ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
282                    ports {
283                        #address-cells = <1>;
284                        #size-cells = <0>;
285                        port@0 {
286                            reg = <0>;
287                            oldi0_in: endpoint {
288                                remote-endpoint = <&dpi0_out0>;
289                            };
290                        };
291                        port@1 {
292                            reg = <1>;
293                            oldi0_out: endpoint {
294                                remote-endpoint = <&panel_in0>;
295                            };
296                        };
297                    };
298                };
299                oldi1: oldi@1 {
300                    reg = <1>;
301                    clocks = <&k3_clks 186 0>;
302                    clock-names = "serial";
303                    ti,secondary-oldi;
304                    ti,companion-oldi = <&oldi0>;
305                    ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
306                    ports {
307                        #address-cells = <1>;
308                        #size-cells = <0>;
309                        port@0 {
310                            reg = <0>;
311                            oldi1_in: endpoint {
312                                remote-endpoint = <&dpi0_out1>;
313                            };
314                        };
315                        port@1 {
316                            reg = <1>;
317                            oldi1_out: endpoint {
318                                remote-endpoint = <&panel_in1>;
319                            };
320                        };
321                    };
322                };
323            };
324            ports {
325                #address-cells = <1>;
326                #size-cells = <0>;
327                port@0 {
328                    #address-cells = <1>;
329                    #size-cells = <0>;
330                    reg = <0>;
331                    dpi0_out0: endpoint@0 {
332                        reg = <0>;
333                        remote-endpoint = <&oldi0_in>;
334                    };
335                    dpi0_out1: endpoint@1 {
336                        reg = <1>;
337                        remote-endpoint = <&oldi1_in>;
338                    };
339                };
340                port@1 {
341                    reg = <1>;
342                    dpi1_out: endpoint {
343                        remote-endpoint = <&hdmi_bridge>;
344                    };
345                };
346            };
347        };
348    };