nvidia,tegra20-mpe.yaml

 1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 2%YAML 1.2
 3---
 4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml#
 5$schema: http://devicetree.org/meta-schemas/core.yaml#
 6
 7title: NVIDIA Tegra Video Encoder
 8
 9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  $nodename:
15    oneOf:
16      - pattern: "^mpe@[0-9a-f]+$"
17      - pattern: "^msenc@[0-9a-f]+$"
18
19  compatible:
20    oneOf:
21      - enum:
22          - nvidia,tegra20-mpe
23          - nvidia,tegra30-mpe
24          - nvidia,tegra114-msenc
25          - nvidia,tegra124-msenc
26
27      - items:
28          - const: nvidia,tegra132-msenc
29          - const: nvidia,tegra124-msenc
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    maxItems: 1
36
37  clocks:
38    items:
39      - description: module clock
40
41  resets:
42    items:
43      - description: module reset
44
45  reset-names:
46    items:
47      - const: mpe
48
49  iommus:
50    maxItems: 1
51
52  interconnects:
53    maxItems: 6
54
55  interconnect-names:
56    maxItems: 6
57
58  operating-points-v2: true
59
60  power-domains:
61    items:
62      - description: phandle to the MPE power domain
63
64additionalProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/clock/tegra20-car.h>
69    #include <dt-bindings/interrupt-controller/arm-gic.h>
70
71    mpe@54040000 {
72        compatible = "nvidia,tegra20-mpe";
73        reg = <0x54040000 0x00040000>;
74        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
75        clocks = <&tegra_car TEGRA20_CLK_MPE>;
76        resets = <&tegra_car 60>;
77        reset-names = "mpe";
78    };