nvidia,tegra114-tsec.yaml

 1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 2%YAML 1.2
 3---
 4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml#
 5$schema: http://devicetree.org/meta-schemas/core.yaml#
 6
 7title: NVIDIA Tegra Security co-processor
 8
 9maintainers:
10  - Svyatoslav Ryhel <clamor95@gmail.com>
11  - Thierry Reding <thierry.reding@gmail.com>
12
13description: Tegra Security co-processor, an embedded security processor used
14  mainly to manage the HDCP encryption and keys on the HDMI link.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - nvidia,tegra114-tsec
21          - nvidia,tegra124-tsec
22          - nvidia,tegra210-tsec
23
24      - items:
25          - const: nvidia,tegra132-tsec
26          - const: nvidia,tegra124-tsec
27
28  reg:
29    maxItems: 1
30
31  interrupts:
32    maxItems: 1
33
34  clocks:
35    maxItems: 1
36
37  resets:
38    maxItems: 1
39
40  iommus:
41    maxItems: 1
42
43  operating-points-v2: true
44
45  power-domains:
46    maxItems: 1
47
48additionalProperties: false
49
50required:
51  - compatible
52  - reg
53  - interrupts
54  - clocks
55  - resets
56
57examples:
58  - |
59    #include <dt-bindings/clock/tegra114-car.h>
60    #include <dt-bindings/interrupt-controller/arm-gic.h>
61
62    tsec@54500000 {
63        compatible = "nvidia,tegra114-tsec";
64        reg = <0x54500000 0x00040000>;
65        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
66        clocks = <&tegra_car TEGRA114_CLK_TSEC>;
67        resets = <&tegra_car TEGRA114_CLK_TSEC>;
68    };