samsung,fimd.yaml

  1# SPDX-License-Identifier: GPL-2.0-only
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/samsung/samsung,fimd.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)
  8
  9maintainers:
 10  - Inki Dae <inki.dae@samsung.com>
 11  - Seung-Woo Kim <sw0312.kim@samsung.com>
 12  - Kyungmin Park <kyungmin.park@samsung.com>
 13  - Krzysztof Kozlowski <krzk@kernel.org>
 14
 15properties:
 16  compatible:
 17    enum:
 18      - samsung,s3c6400-fimd
 19      - samsung,s5pv210-fimd
 20      - samsung,exynos3250-fimd
 21      - samsung,exynos4210-fimd
 22      - samsung,exynos5250-fimd
 23      - samsung,exynos5420-fimd
 24
 25  '#address-cells':
 26    const: 1
 27
 28  clocks:
 29    maxItems: 2
 30
 31  clock-names:
 32    items:
 33      - const: sclk_fimd
 34      - const: fimd
 35
 36  display-timings:
 37    $ref: ../panel/display-timings.yaml#
 38
 39  i80-if-timings:
 40    type: object
 41    additionalProperties: false
 42    description: |
 43      Timing configuration for lcd i80 interface support.
 44      The parameters are defined as::
 45      VCLK(internal)  __|??????|_____|??????|_____|??????|_____|??????|_____|??
 46                        :            :            :            :            :
 47      Address Output  --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
 48                        | cs-setup+1 |            :            :            :
 49                        |<---------->|            :            :            :
 50      Chip Select     ???????????????|____________:____________:____________|??
 51                                     | wr-setup+1 |            | wr-hold+1  |
 52                                     |<---------->|            |<---------->|
 53      Write Enable    ????????????????????????????|____________|???????????????
 54                                                  | wr-active+1|
 55                                                  |<---------->|
 56      Video Data      ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
 57
 58    properties:
 59      cs-setup:
 60        $ref: /schemas/types.yaml#/definitions/uint32
 61        description:
 62          Clock cycles for the active period of address signal is enabled until
 63          chip select is enabled.
 64        default: 0
 65
 66      wr-active:
 67        $ref: /schemas/types.yaml#/definitions/uint32
 68        description:
 69          Clock cycles for the active period of CS is enabled.
 70        default: 1
 71
 72      wr-hold:
 73        $ref: /schemas/types.yaml#/definitions/uint32
 74        description:
 75          Clock cycles for the active period of CS is disabled until write
 76          signal is disabled.
 77        default: 0
 78
 79      wr-setup:
 80        $ref: /schemas/types.yaml#/definitions/uint32
 81        description:
 82          Clock cycles for the active period of CS signal is enabled until
 83          write signal is enabled.
 84        default: 0
 85
 86  iommus:
 87    minItems: 1
 88    maxItems: 2
 89
 90  iommu-names:
 91    items:
 92      - const: m0
 93      - const: m1
 94
 95  interrupts:
 96    items:
 97      - description: FIFO level
 98      - description: VSYNC
 99      - description: LCD system
100
101  interrupt-names:
102    items:
103      - const: fifo
104      - const: vsync
105      - const: lcd_sys
106
107  power-domains:
108    maxItems: 1
109
110  reg:
111    maxItems: 1
112
113  samsung,invert-vden:
114    type: boolean
115    description:
116      Video enable signal is inverted.
117
118  samsung,invert-vclk:
119    type: boolean
120    description:
121      Video clock signal is inverted.
122
123  samsung,sysreg:
124    $ref: /schemas/types.yaml#/definitions/phandle
125    description:
126      Phandle to System Register syscon.
127
128  '#size-cells':
129    const: 0
130
131patternProperties:
132  "^port@[0-4]+$":
133    $ref: /schemas/graph.yaml#/properties/port
134    description: |
135      Contains ports with port with index::
136       0 - for CAMIF0 input,
137       1 - for CAMIF1 input,
138       2 - for CAMIF2 input,
139       3 - for parallel output,
140       4 - for write-back interface
141
142required:
143  - compatible
144  - clocks
145  - clock-names
146  - interrupts
147  - interrupt-names
148  - reg
149
150allOf:
151  - if:
152      properties:
153        compatible:
154          contains:
155            const: samsung,exynos5420-fimd
156    then:
157      properties:
158        iommus:
159          minItems: 2
160          maxItems: 2
161
162additionalProperties: false
163
164examples:
165  - |
166    #include <dt-bindings/clock/exynos4.h>
167
168    fimd@11c00000 {
169        compatible = "samsung,exynos4210-fimd";
170        interrupt-parent = <&combiner>;
171        reg = <0x11c00000 0x20000>;
172        interrupt-names = "fifo", "vsync", "lcd_sys";
173        interrupts = <11 0>, <11 1>, <11 2>;
174        clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
175        clock-names = "sclk_fimd", "fimd";
176        power-domains = <&pd_lcd0>;
177        iommus = <&sysmmu_fimd0>;
178        samsung,sysreg = <&sys_reg>;
179
180        #address-cells = <1>;
181        #size-cells = <0>;
182
183        samsung,invert-vden;
184        samsung,invert-vclk;
185
186        pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
187        pinctrl-names = "default";
188
189        port@3 {
190            reg = <3>;
191
192            fimd_dpi_ep: endpoint {
193                remote-endpoint = <&lcd_ep>;
194            };
195        };
196    };