samsung,exynos7-decon.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
  8
  9maintainers:
 10  - Inki Dae <inki.dae@samsung.com>
 11  - Seung-Woo Kim <sw0312.kim@samsung.com>
 12  - Kyungmin Park <kyungmin.park@samsung.com>
 13  - Krzysztof Kozlowski <krzk@kernel.org>
 14
 15description: |
 16  DECON (Display and Enhancement Controller) is the Display Controller for the
 17  Exynos7 series of SoCs which transfers the image data from a video memory
 18  buffer to an external LCD interface.
 19
 20properties:
 21  compatible:
 22    enum:
 23      - samsung,exynos7-decon
 24      - samsung,exynos7870-decon
 25
 26  clocks:
 27    maxItems: 4
 28
 29  clock-names:
 30    items:
 31      - const: pclk_decon0
 32      - const: aclk_decon0
 33      - const: decon0_eclk
 34      - const: decon0_vclk
 35
 36  display-timings:
 37    $ref: ../panel/display-timings.yaml#
 38
 39  i80-if-timings:
 40    type: object
 41    additionalProperties: false
 42    description: timing configuration for lcd i80 interface support
 43    properties:
 44      cs-setup:
 45        $ref: /schemas/types.yaml#/definitions/uint32
 46        description:
 47          Clock cycles for the active period of address signal is enabled until
 48          chip select is enabled.
 49        default: 0
 50
 51      wr-active:
 52        $ref: /schemas/types.yaml#/definitions/uint32
 53        description:
 54          Clock cycles for the active period of CS is enabled.
 55        default: 1
 56
 57      wr-hold:
 58        $ref: /schemas/types.yaml#/definitions/uint32
 59        description:
 60          Clock cycles for the active period of CS is disabled until write
 61          signal is disabled.
 62        default: 0
 63
 64      wr-setup:
 65        $ref: /schemas/types.yaml#/definitions/uint32
 66        description:
 67          Clock cycles for the active period of CS signal is enabled until
 68          write signal is enabled.
 69        default: 0
 70
 71  interrupts:
 72    items:
 73      - description: FIFO level
 74      - description: VSYNC
 75      - description: LCD system
 76
 77  interrupt-names:
 78    items:
 79      - const: fifo
 80      - const: vsync
 81      - const: lcd_sys
 82
 83  iommus:
 84    maxItems: 1
 85
 86  memory-region:
 87    maxItems: 1
 88    description:
 89      A phandle to a node describing a reserved framebuffer memory region.
 90      For example, the splash memory region set up by the bootloader.
 91
 92  port:
 93    $ref: /schemas/graph.yaml#/properties/port
 94    description:
 95      Output port which is connected to either a Mobile Image Compressor
 96      (MIC) or a DSI Master device.
 97
 98  power-domains:
 99    maxItems: 1
100
101  reg:
102    maxItems: 1
103
104required:
105  - compatible
106  - clocks
107  - clock-names
108  - interrupts
109  - interrupt-names
110  - port
111  - reg
112
113additionalProperties: false
114
115examples:
116  - |
117    #include <dt-bindings/clock/exynos7-clk.h>
118    #include <dt-bindings/interrupt-controller/arm-gic.h>
119
120    display-controller@13930000 {
121        compatible = "samsung,exynos7-decon";
122        reg = <0x13930000 0x1000>;
123        interrupt-names = "fifo", "vsync", "lcd_sys";
124        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
125                     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
126                     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
127        clocks = <&clock_disp 100>, /* PCLK_DECON_INT */
128                 <&clock_disp 101>, /* ACLK_DECON_INT */
129                 <&clock_disp 102>, /* SCLK_DECON_INT_ECLK */
130                 <&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */
131        clock-names = "pclk_decon0",
132                      "aclk_decon0",
133                      "decon0_eclk",
134                      "decon0_vclk";
135        pinctrl-0 = <&lcd_clk &pwm1_out>;
136        pinctrl-names = "default";
137        port {
138            decon_to_dsi: endpoint {
139                remote-endpoint = <&dsi_to_decon>;
140            };
141        };
142    };