rockchip,rk3588-mipi-dsi2.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Rockchip specific extensions to the Synopsys Designware MIPI DSI2
  8
  9maintainers:
 10  - Heiko Stuebner <heiko@sntech.de>
 11
 12properties:
 13  compatible:
 14    enum:
 15      - rockchip,rk3576-mipi-dsi2
 16      - rockchip,rk3588-mipi-dsi2
 17
 18  reg:
 19    maxItems: 1
 20
 21  interrupts:
 22    maxItems: 1
 23
 24  clocks:
 25    maxItems: 2
 26
 27  clock-names:
 28    items:
 29      - const: pclk
 30      - const: sys
 31
 32  rockchip,grf:
 33    $ref: /schemas/types.yaml#/definitions/phandle
 34    description:
 35      This SoC uses GRF regs to switch between vopl/vopb.
 36
 37  phys:
 38    maxItems: 1
 39
 40  phy-names:
 41    const: dcphy
 42
 43  power-domains:
 44    maxItems: 1
 45
 46  resets:
 47    maxItems: 1
 48
 49  reset-names:
 50    const: apb
 51
 52  ports:
 53    $ref: /schemas/graph.yaml#/properties/ports
 54
 55    properties:
 56      port@0:
 57        $ref: /schemas/graph.yaml#/properties/port
 58        description: Input node to receive pixel data.
 59
 60      port@1:
 61        $ref: /schemas/graph.yaml#/properties/port
 62        description: DSI output node to panel.
 63
 64    required:
 65      - port@0
 66      - port@1
 67
 68required:
 69  - compatible
 70  - clocks
 71  - clock-names
 72  - rockchip,grf
 73  - phys
 74  - phy-names
 75  - ports
 76  - reg
 77
 78allOf:
 79  - $ref: /schemas/display/dsi-controller.yaml#
 80
 81unevaluatedProperties: false
 82
 83examples:
 84  - |
 85    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
 86    #include <dt-bindings/interrupt-controller/arm-gic.h>
 87    #include <dt-bindings/interrupt-controller/irq.h>
 88    #include <dt-bindings/phy/phy.h>
 89    #include <dt-bindings/power/rk3588-power.h>
 90    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
 91
 92    soc {
 93      #address-cells = <2>;
 94      #size-cells = <2>;
 95
 96      dsi@fde20000 {
 97        compatible = "rockchip,rk3588-mipi-dsi2";
 98        reg = <0x0 0xfde20000 0x0 0x10000>;
 99        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
100        clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
101        clock-names = "pclk", "sys";
102        resets = <&cru SRST_P_DSIHOST0>;
103        reset-names = "apb";
104        power-domains = <&power RK3588_PD_VOP>;
105        phys = <&mipidcphy0 PHY_TYPE_DPHY>;
106        phy-names = "dcphy";
107        rockchip,grf = <&vop_grf>;
108
109        ports {
110          #address-cells = <1>;
111          #size-cells = <0>;
112          dsi0_in: port@0 {
113            reg = <0>;
114          };
115
116          dsi0_out: port@1 {
117            reg = <1>;
118          };
119        };
120      };
121    };