rockchip,rk3588-dw-hdmi-qp.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Rockchip DW HDMI QP TX Encoder
  8
  9maintainers:
 10  - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
 11
 12description: |
 13  Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI QP TX controller
 14  IP and a HDMI/eDP TX Combo PHY based on a Samsung IP block, providing the
 15  following features, among others:
 16
 17  * Fixed Rate Link (FRL)
 18  * Display Stream Compression (DSC)
 19  * 4K@120Hz and 8K@60Hz video modes
 20  * Variable Refresh Rate (VRR) including Quick Media Switching (QMS)
 21  * Fast Vactive (FVA)
 22  * SCDC I2C DDC access
 23  * Multi-stream audio
 24  * Enhanced Audio Return Channel (EARC)
 25
 26allOf:
 27  - $ref: /schemas/sound/dai-common.yaml#
 28
 29properties:
 30  compatible:
 31    enum:
 32      - rockchip,rk3576-dw-hdmi-qp
 33      - rockchip,rk3588-dw-hdmi-qp
 34
 35  reg:
 36    maxItems: 1
 37
 38  clocks:
 39    items:
 40      - description: Peripheral/APB bus clock
 41      - description: EARC RX biphase clock
 42      - description: Reference clock
 43      - description: Audio interface clock
 44      - description: TMDS/FRL link clock
 45      - description: Video datapath clock
 46
 47  clock-names:
 48    items:
 49      - const: pclk
 50      - const: earc
 51      - const: ref
 52      - const: aud
 53      - const: hdp
 54      - const: hclk_vo1
 55
 56  interrupts:
 57    items:
 58      - description: AVP Unit interrupt
 59      - description: CEC interrupt
 60      - description: eARC RX interrupt
 61      - description: Main Unit interrupt
 62      - description: HPD interrupt
 63
 64  interrupt-names:
 65    items:
 66      - const: avp
 67      - const: cec
 68      - const: earc
 69      - const: main
 70      - const: hpd
 71
 72  phys:
 73    maxItems: 1
 74    description: The HDMI/eDP PHY
 75
 76  ports:
 77    $ref: /schemas/graph.yaml#/properties/ports
 78
 79    properties:
 80      port@0:
 81        $ref: /schemas/graph.yaml#/properties/port
 82        description: Video port for RGB/YUV input.
 83
 84      port@1:
 85        $ref: /schemas/graph.yaml#/properties/port
 86        description: Video port for HDMI/eDP output.
 87
 88    required:
 89      - port@0
 90      - port@1
 91
 92  power-domains:
 93    maxItems: 1
 94
 95  resets:
 96    maxItems: 2
 97
 98  reset-names:
 99    items:
100      - const: ref
101      - const: hdp
102
103  "#sound-dai-cells":
104    const: 0
105
106  rockchip,grf:
107    $ref: /schemas/types.yaml#/definitions/phandle
108    description:
109      Some HDMI QP related data is accessed through SYS GRF regs.
110
111  rockchip,vo-grf:
112    $ref: /schemas/types.yaml#/definitions/phandle
113    description:
114      Additional HDMI QP related data is accessed through VO GRF regs.
115
116  frl-enable-gpios:
117    description:
118      Optional GPIO line to be asserted when operating in HDMI 2.1 FRL mode and
119      deasserted for HDMI 1.4/2.0 TMDS. It can be used to control external
120      voltage bias for HDMI data lines. When not present the HDMI encoder will
121      operate in TMDS mode only.
122    maxItems: 1
123
124required:
125  - compatible
126  - reg
127  - clocks
128  - clock-names
129  - interrupts
130  - interrupt-names
131  - phys
132  - ports
133  - resets
134  - reset-names
135  - rockchip,grf
136  - rockchip,vo-grf
137
138unevaluatedProperties: false
139
140examples:
141  - |
142    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
143    #include <dt-bindings/gpio/gpio.h>
144    #include <dt-bindings/interrupt-controller/arm-gic.h>
145    #include <dt-bindings/interrupt-controller/irq.h>
146    #include <dt-bindings/pinctrl/rockchip.h>
147    #include <dt-bindings/power/rk3588-power.h>
148    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
149
150    soc {
151      #address-cells = <2>;
152      #size-cells = <2>;
153
154      hdmi@fde80000 {
155        compatible = "rockchip,rk3588-dw-hdmi-qp";
156        reg = <0x0 0xfde80000 0x0 0x20000>;
157        clocks = <&cru PCLK_HDMITX0>,
158                 <&cru CLK_HDMITX0_EARC>,
159                 <&cru CLK_HDMITX0_REF>,
160                 <&cru MCLK_I2S5_8CH_TX>,
161                 <&cru CLK_HDMIHDP0>,
162                 <&cru HCLK_VO1>;
163        clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
164        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
165                     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
166                     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
167                     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
168                     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
169        interrupt-names = "avp", "cec", "earc", "main", "hpd";
170        phys = <&hdptxphy0>;
171        power-domains = <&power RK3588_PD_VO1>;
172        resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
173        reset-names = "ref", "hdp";
174        rockchip,grf = <&sys_grf>;
175        rockchip,vo-grf = <&vo1_grf>;
176        #sound-dai-cells = <0>;
177        frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
178
179        ports {
180          #address-cells = <1>;
181          #size-cells = <0>;
182
183          port@0 {
184            reg = <0>;
185
186            hdmi0_in_vp0: endpoint {
187              remote-endpoint = <&vp0_out_hdmi0>;
188            };
189          };
190
191          port@1 {
192            reg = <1>;
193
194            hdmi0_out_con0: endpoint {
195              remote-endpoint = <&hdmi_con0_in>;
196            };
197          };
198        };
199      };
200    };