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rockchip,analogix-dp.yaml

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linux-6.19.14/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml YAML
  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Rockchip specific extensions to the Analogix Display Port
  8
  9maintainers:
 10  - Sandy Huang <hjc@rock-chips.com>
 11  - Heiko Stuebner <heiko@sntech.de>
 12
 13properties:
 14  compatible:
 15    enum:
 16      - rockchip,rk3288-dp
 17      - rockchip,rk3399-edp
 18      - rockchip,rk3588-edp
 19
 20  clocks:
 21    minItems: 2
 22    maxItems: 3
 23
 24  clock-names:
 25    minItems: 2
 26    items:
 27      - const: dp
 28      - const: pclk
 29      - const: grf
 30
 31  power-domains:
 32    maxItems: 1
 33
 34  resets:
 35    minItems: 1
 36    maxItems: 2
 37
 38  reset-names:
 39    minItems: 1
 40    items:
 41      - const: dp
 42      - const: apb
 43
 44  rockchip,grf:
 45    $ref: /schemas/types.yaml#/definitions/phandle
 46    description:
 47      This SoC makes use of GRF regs.
 48
 49  aux-bus:
 50    $ref: /schemas/display/dp-aux-bus.yaml#
 51
 52required:
 53  - compatible
 54  - clocks
 55  - clock-names
 56  - resets
 57  - reset-names
 58  - rockchip,grf
 59
 60allOf:
 61  - $ref: /schemas/display/bridge/analogix,dp.yaml#
 62
 63  - if:
 64      properties:
 65        compatible:
 66          contains:
 67            enum:
 68              - rockchip,rk3588-edp
 69    then:
 70      properties:
 71        resets:
 72          minItems: 2
 73        reset-names:
 74          minItems: 2
 75
 76unevaluatedProperties: false
 77
 78examples:
 79  - |
 80    #include <dt-bindings/clock/rk3288-cru.h>
 81    #include <dt-bindings/interrupt-controller/arm-gic.h>
 82    #include <dt-bindings/interrupt-controller/irq.h>
 83    dp@ff970000 {
 84      compatible = "rockchip,rk3288-dp";
 85      reg = <0xff970000 0x4000>;
 86      interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 87      clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
 88      clock-names = "dp", "pclk";
 89      phys = <&dp_phy>;
 90      phy-names = "dp";
 91      resets = <&cru 111>;
 92      reset-names = "dp";
 93      rockchip,grf = <&grf>;
 94      pinctrl-0 = <&edp_hpd>;
 95      pinctrl-names = "default";
 96
 97      ports {
 98        #address-cells = <1>;
 99        #size-cells = <0>;
100
101        edp_in: port@0 {
102          reg = <0>;
103          #address-cells = <1>;
104          #size-cells = <0>;
105
106          edp_in_vopb: endpoint@0 {
107            reg = <0>;
108            remote-endpoint = <&vopb_out_edp>;
109          };
110          edp_in_vopl: endpoint@1 {
111            reg = <1>;
112            remote-endpoint = <&vopl_out_edp>;
113          };
114        };
115
116        edp_out: port@1 {
117          reg = <1>;
118
119          edp_out_panel: endpoint {
120            remote-endpoint = <&panel_in_edp>;
121          };
122        };
123      };
124    };
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