renesas,rzg2l-du.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Renesas RZ/G2L Display Unit (DU)
  8
  9maintainers:
 10  - Biju Das <biju.das.jz@bp.renesas.com>
 11  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
 12
 13description: |
 14  These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
 15  and RZ/V2L SoCs.
 16
 17properties:
 18  compatible:
 19    oneOf:
 20      - enum:
 21          - renesas,r9a07g043u-du # RZ/G2UL
 22          - renesas,r9a07g044-du # RZ/G2{L,LC}
 23          - renesas,r9a09g057-du # RZ/V2H(P)
 24      - items:
 25          - enum:
 26              - renesas,r9a07g054-du    # RZ/V2L
 27          - const: renesas,r9a07g044-du # RZ/G2L fallback
 28      - items:
 29          - const: renesas,r9a09g056-du # RZ/V2N
 30          - const: renesas,r9a09g057-du # RZ/V2H(P) fallback
 31
 32  reg:
 33    maxItems: 1
 34
 35  interrupts:
 36    maxItems: 1
 37
 38  clocks:
 39    items:
 40      - description: Main clock
 41      - description: Register access clock
 42      - description: Video clock
 43
 44  clock-names:
 45    items:
 46      - const: aclk
 47      - const: pclk
 48      - const: vclk
 49
 50  resets:
 51    maxItems: 1
 52
 53  power-domains:
 54    maxItems: 1
 55
 56  ports:
 57    $ref: /schemas/graph.yaml#/properties/ports
 58    description: |
 59      The connections to the DU output video ports are modeled using the OF
 60      graph bindings. The number of ports and their assignment are
 61      model-dependent. Each port shall have a single endpoint.
 62
 63    patternProperties:
 64      "^port@[0-1]$":
 65        $ref: /schemas/graph.yaml#/properties/port
 66        unevaluatedProperties: false
 67
 68    unevaluatedProperties: false
 69
 70  renesas,vsps:
 71    $ref: /schemas/types.yaml#/definitions/phandle-array
 72    items:
 73      items:
 74        - description: phandle to VSP instance that serves the DU channel
 75        - description: Channel index identifying the LIF instance in that VSP
 76    description:
 77      A list of phandle and channel index tuples to the VSPs that handle the
 78      memory interfaces for the DU channels.
 79
 80required:
 81  - compatible
 82  - reg
 83  - interrupts
 84  - clocks
 85  - clock-names
 86  - resets
 87  - power-domains
 88  - ports
 89  - renesas,vsps
 90
 91additionalProperties: false
 92
 93allOf:
 94  - if:
 95      properties:
 96        compatible:
 97          contains:
 98            const: renesas,r9a07g043u-du
 99    then:
100      properties:
101        ports:
102          properties:
103            port@0:
104              description: DPI
105
106          required:
107            - port@0
108  - if:
109      properties:
110        compatible:
111          contains:
112            const: renesas,r9a07g044-du
113    then:
114      properties:
115        ports:
116          properties:
117            port@0:
118              description: DSI
119            port@1:
120              description: DPI
121
122          required:
123            - port@0
124            - port@1
125  - if:
126      properties:
127        compatible:
128          contains:
129            const: renesas,r9a09g057-du
130    then:
131      properties:
132        ports:
133          properties:
134            port@0:
135              description: DSI
136            port@1: false
137
138          required:
139            - port@0
140
141examples:
142  # RZ/G2L DU
143  - |
144    #include <dt-bindings/clock/r9a07g044-cpg.h>
145    #include <dt-bindings/interrupt-controller/arm-gic.h>
146
147    display@10890000 {
148        compatible = "renesas,r9a07g044-du";
149        reg = <0x10890000 0x10000>;
150        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
151        clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
152                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
153                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
154        clock-names = "aclk", "pclk", "vclk";
155        resets = <&cpg R9A07G044_LCDC_RESET_N>;
156        power-domains = <&cpg>;
157
158        renesas,vsps = <&vspd0 0>;
159
160        ports {
161            #address-cells = <1>;
162            #size-cells = <0>;
163
164            port@0 {
165                reg = <0>;
166                endpoint {
167                    remote-endpoint = <&dsi0_in>;
168                };
169            };
170            port@1 {
171                reg = <1>;
172            };
173        };
174    };
175
176...