qcom,sm8650-dpu.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SM8650 Display DPU
  8
  9maintainers:
 10  - Neil Armstrong <neil.armstrong@linaro.org>
 11
 12$ref: /schemas/display/msm/dpu-common.yaml#
 13
 14properties:
 15  compatible:
 16    oneOf:
 17      - enum:
 18          - qcom,glymur-dpu
 19          - qcom,sa8775p-dpu
 20          - qcom,sm8650-dpu
 21          - qcom,sm8750-dpu
 22          - qcom,x1e80100-dpu
 23      - items:
 24          - enum:
 25              - qcom,qcs8300-dpu
 26          - const: qcom,sa8775p-dpu
 27
 28  reg:
 29    items:
 30      - description: Address offset and size for mdp register set
 31      - description: Address offset and size for vbif register set
 32
 33  reg-names:
 34    items:
 35      - const: mdp
 36      - const: vbif
 37
 38  clocks:
 39    items:
 40      - description: Display hf axi
 41      - description: Display MDSS ahb
 42      - description: Display lut
 43      - description: Display core
 44      - description: Display vsync
 45
 46  clock-names:
 47    items:
 48      - const: nrt_bus
 49      - const: iface
 50      - const: lut
 51      - const: core
 52      - const: vsync
 53
 54required:
 55  - compatible
 56  - reg
 57  - reg-names
 58  - clocks
 59  - clock-names
 60
 61unevaluatedProperties: false
 62
 63examples:
 64  - |
 65    #include <dt-bindings/interrupt-controller/arm-gic.h>
 66    #include <dt-bindings/power/qcom,rpmhpd.h>
 67
 68    display-controller@ae01000 {
 69        compatible = "qcom,sm8650-dpu";
 70        reg = <0x0ae01000 0x8f000>,
 71              <0x0aeb0000 0x2008>;
 72        reg-names = "mdp", "vbif";
 73
 74        clocks = <&gcc_axi_clk>,
 75                 <&dispcc_ahb_clk>,
 76                 <&dispcc_mdp_lut_clk>,
 77                 <&dispcc_mdp_clk>,
 78                 <&dispcc_vsync_clk>;
 79        clock-names = "nrt_bus",
 80                      "iface",
 81                      "lut",
 82                      "core",
 83                      "vsync";
 84
 85        assigned-clocks = <&dispcc_vsync_clk>;
 86        assigned-clock-rates = <19200000>;
 87
 88        operating-points-v2 = <&mdp_opp_table>;
 89        power-domains = <&rpmhpd RPMHPD_MMCX>;
 90
 91        interrupt-parent = <&mdss>;
 92        interrupts = <0>;
 93
 94        ports {
 95            #address-cells = <1>;
 96            #size-cells = <0>;
 97
 98            port@0 {
 99                reg = <0>;
100                dpu_intf1_out: endpoint {
101                    remote-endpoint = <&dsi0_in>;
102                };
103            };
104
105            port@1 {
106                reg = <1>;
107                dpu_intf2_out: endpoint {
108                    remote-endpoint = <&dsi1_in>;
109                };
110            };
111        };
112
113        mdp_opp_table: opp-table {
114            compatible = "operating-points-v2";
115
116            opp-200000000 {
117                opp-hz = /bits/ 64 <200000000>;
118                required-opps = <&rpmhpd_opp_low_svs>;
119            };
120
121            opp-325000000 {
122                opp-hz = /bits/ 64 <325000000>;
123                required-opps = <&rpmhpd_opp_svs>;
124            };
125
126            opp-375000000 {
127                opp-hz = /bits/ 64 <375000000>;
128                required-opps = <&rpmhpd_opp_svs_l1>;
129            };
130
131            opp-514000000 {
132                opp-hz = /bits/ 64 <514000000>;
133                required-opps = <&rpmhpd_opp_nom>;
134            };
135        };
136    };
137...