qcom,sm6375-mdss.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SM6375 Display MDSS
  8
  9maintainers:
 10  - Konrad Dybcio <konradybcio@kernel.org>
 11
 12description:
 13  SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
 14  like DPU display controller, DSI and DP interfaces etc.
 15
 16$ref: /schemas/display/msm/mdss-common.yaml#
 17
 18properties:
 19  compatible:
 20    const: qcom,sm6375-mdss
 21
 22  clocks:
 23    items:
 24      - description: Display AHB clock from gcc
 25      - description: Display AHB clock
 26      - description: Display core clock
 27
 28  clock-names:
 29    items:
 30      - const: iface
 31      - const: ahb
 32      - const: core
 33
 34  iommus:
 35    maxItems: 1
 36
 37  interconnects:
 38    items:
 39      - description: Interconnect path from mdp0 port to the data bus
 40      - description: Interconnect path from CPU to the reg bus
 41
 42  interconnect-names:
 43    items:
 44      - const: mdp0-mem
 45      - const: cpu-cfg
 46
 47patternProperties:
 48  "^display-controller@[0-9a-f]+$":
 49    type: object
 50    additionalProperties: true
 51
 52    properties:
 53      compatible:
 54        const: qcom,sm6375-dpu
 55
 56  "^dsi@[0-9a-f]+$":
 57    type: object
 58    additionalProperties: true
 59
 60    properties:
 61      compatible:
 62        items:
 63          - const: qcom,sm6375-dsi-ctrl
 64          - const: qcom,mdss-dsi-ctrl
 65
 66  "^phy@[0-9a-f]+$":
 67    type: object
 68    additionalProperties: true
 69
 70    properties:
 71      compatible:
 72        const: qcom,sm6375-dsi-phy-7nm
 73
 74unevaluatedProperties: false
 75
 76examples:
 77  - |
 78    #include <dt-bindings/clock/qcom,rpmcc.h>
 79    #include <dt-bindings/clock/qcom,sm6375-gcc.h>
 80    #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
 81    #include <dt-bindings/interrupt-controller/arm-gic.h>
 82    #include <dt-bindings/power/qcom-rpmpd.h>
 83
 84    display-subsystem@5e00000 {
 85        compatible = "qcom,sm6375-mdss";
 86        reg = <0x05e00000 0x1000>;
 87        reg-names = "mdss";
 88
 89        power-domains = <&dispcc MDSS_GDSC>;
 90
 91        clocks = <&gcc GCC_DISP_AHB_CLK>,
 92                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
 93                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
 94        clock-names = "iface", "ahb", "core";
 95
 96        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 97        interrupt-controller;
 98        #interrupt-cells = <1>;
 99
100        iommus = <&apps_smmu 0x820 0x2>;
101        #address-cells = <1>;
102        #size-cells = <1>;
103        ranges;
104
105        display-controller@5e01000 {
106            compatible = "qcom,sm6375-dpu";
107            reg = <0x05e01000 0x8e030>,
108                  <0x05eb0000 0x2008>;
109            reg-names = "mdp", "vbif";
110
111            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
112                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
113                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
114                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
115                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
116                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
117                     <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
118            clock-names = "bus",
119                          "iface",
120                          "rot",
121                          "lut",
122                          "core",
123                          "vsync",
124                          "throttle";
125
126            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
127            assigned-clock-rates = <19200000>;
128
129            operating-points-v2 = <&mdp_opp_table>;
130            power-domains = <&rpmpd SM6375_VDDCX>;
131
132            interrupt-parent = <&mdss>;
133            interrupts = <0>;
134
135            ports {
136                #address-cells = <1>;
137                #size-cells = <0>;
138
139                port@0 {
140                    reg = <0>;
141                    dpu_intf1_out: endpoint {
142                        remote-endpoint = <&dsi0_in>;
143                    };
144                };
145            };
146        };
147
148        dsi@5e94000 {
149            compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
150            reg = <0x05e94000 0x400>;
151            reg-names = "dsi_ctrl";
152
153            interrupt-parent = <&mdss>;
154            interrupts = <4>;
155
156            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
157                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
158                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
159                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
160                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
161                     <&gcc GCC_DISP_HF_AXI_CLK>;
162            clock-names = "byte",
163                          "byte_intf",
164                          "pixel",
165                          "core",
166                          "iface",
167                          "bus";
168
169            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
170                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
171            assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
172
173            operating-points-v2 = <&dsi_opp_table>;
174            power-domains = <&rpmpd SM6375_VDDMX>;
175
176            phys = <&mdss_dsi0_phy>;
177            phy-names = "dsi";
178
179            #address-cells = <1>;
180            #size-cells = <0>;
181
182            ports {
183                #address-cells = <1>;
184                #size-cells = <0>;
185
186                port@0 {
187                    reg = <0>;
188                    dsi0_in: endpoint {
189                        remote-endpoint = <&dpu_intf1_out>;
190                    };
191                };
192
193                port@1 {
194                    reg = <1>;
195                    dsi0_out: endpoint {
196                    };
197                };
198            };
199        };
200
201        mdss_dsi0_phy: phy@5e94400 {
202            compatible = "qcom,sm6375-dsi-phy-7nm";
203            reg = <0x05e94400 0x200>,
204                  <0x05e94600 0x280>,
205                  <0x05e94900 0x264>;
206            reg-names = "dsi_phy",
207                        "dsi_phy_lane",
208                        "dsi_pll";
209
210            #clock-cells = <1>;
211            #phy-cells = <0>;
212
213            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
214                     <&rpmcc RPM_SMD_XO_CLK_SRC>;
215            clock-names = "iface", "ref";
216        };
217    };
218...