qcom,sm6150-mdss.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-mdss.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SM6150 Display MDSS
  8
  9maintainers:
 10  - Abhinav Kumar <quic_abhinavk@quicinc.com>
 11  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 12
 13description:
 14  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
 15  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
 16  bindings of MDSS are mentioned for SM6150 target.
 17
 18$ref: /schemas/display/msm/mdss-common.yaml#
 19
 20properties:
 21  compatible:
 22    items:
 23      - const: qcom,sm6150-mdss
 24
 25  clocks:
 26    items:
 27      - description: Display AHB clock from gcc
 28      - description: Display hf axi clock
 29      - description: Display core clock
 30
 31  clock-names:
 32    items:
 33      - const: iface
 34      - const: bus
 35      - const: core
 36
 37  iommus:
 38    maxItems: 1
 39
 40  interconnects:
 41    maxItems: 2
 42
 43  interconnect-names:
 44    maxItems: 2
 45
 46patternProperties:
 47  "^display-controller@[0-9a-f]+$":
 48    type: object
 49    additionalProperties: true
 50    properties:
 51      compatible:
 52        const: qcom,sm6150-dpu
 53
 54  "^displayport-controller@[0-9a-f]+$":
 55    type: object
 56    additionalProperties: true
 57    properties:
 58      compatible:
 59        contains:
 60          const: qcom,sm6150-dp
 61
 62  "^dsi@[0-9a-f]+$":
 63    type: object
 64    additionalProperties: true
 65    properties:
 66      compatible:
 67        items:
 68          - const: qcom,sm6150-dsi-ctrl
 69          - const: qcom,mdss-dsi-ctrl
 70
 71  "^phy@[0-9a-f]+$":
 72    type: object
 73    additionalProperties: true
 74    properties:
 75      compatible:
 76        const: qcom,sm6150-dsi-phy-14nm
 77
 78unevaluatedProperties: false
 79
 80examples:
 81  - |
 82    #include <dt-bindings/clock/qcom,rpmh.h>
 83    #include <dt-bindings/interconnect/qcom,icc.h>
 84    #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
 85    #include <dt-bindings/interrupt-controller/arm-gic.h>
 86    #include <dt-bindings/power/qcom,rpmhpd.h>
 87
 88    display-subsystem@ae00000 {
 89        #address-cells = <1>;
 90        #size-cells = <1>;
 91        compatible = "qcom,sm6150-mdss";
 92        reg = <0x0ae00000 0x1000>;
 93        reg-names = "mdss";
 94
 95        interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
 96                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 97                        <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
 98                         &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
 99        interconnect-names = "mdp0-mem", "cpu-cfg";
100
101        power-domains = <&dispcc_mdss_gdsc>;
102
103        clocks = <&dispcc_mdss_ahb_clk>,
104                 <&gcc_disp_hf_axi_clk>,
105                 <&dispcc_mdss_mdp_clk>;
106
107        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
108        interrupt-controller;
109        #interrupt-cells = <1>;
110
111        iommus = <&apps_smmu 0x800 0x0>;
112
113        ranges;
114
115        display-controller@ae01000 {
116            compatible = "qcom,sm6150-dpu";
117            reg = <0x0ae01000 0x8f000>,
118                  <0x0aeb0000 0x2008>;
119            reg-names = "mdp", "vbif";
120
121            clocks = <&dispcc_mdss_ahb_clk>,
122                     <&gcc_disp_hf_axi_clk>,
123                     <&dispcc_mdss_mdp_clk>,
124                     <&dispcc_mdss_vsync_clk>;
125            clock-names = "iface", "bus", "core", "vsync";
126
127            assigned-clocks = <&dispcc_mdss_vsync_clk>;
128            assigned-clock-rates = <19200000>;
129
130            operating-points-v2 = <&mdp_opp_table>;
131            power-domains = <&rpmhpd RPMHPD_CX>;
132
133            interrupt-parent = <&mdss>;
134            interrupts = <0>;
135
136            ports {
137                #address-cells = <1>;
138                #size-cells = <0>;
139
140                port@0 {
141                    reg = <0>;
142
143                    dpu_intf0_out: endpoint {
144                    };
145                };
146
147                port@1 {
148                    reg = <1>;
149
150                    dpu_intf1_out: endpoint {
151                        remote-endpoint = <&mdss_dsi0_in>;
152                    };
153                };
154            };
155
156            mdp_opp_table: opp-table {
157                compatible = "operating-points-v2";
158
159                opp-192000000 {
160                    opp-hz = /bits/ 64 <192000000>;
161                    required-opps = <&rpmhpd_opp_low_svs>;
162                };
163
164                opp-256000000 {
165                    opp-hz = /bits/ 64 <256000000>;
166                    required-opps = <&rpmhpd_opp_svs>;
167                };
168
169                opp-307200000 {
170                    opp-hz = /bits/ 64 <307200000>;
171                    required-opps = <&rpmhpd_opp_nom>;
172                };
173            };
174        };
175
176        dsi@ae94000 {
177            compatible = "qcom,sm6150-dsi-ctrl",
178                         "qcom,mdss-dsi-ctrl";
179            reg = <0x0ae94000 0x400>;
180            reg-names = "dsi_ctrl";
181
182            interrupt-parent = <&mdss>;
183            interrupts = <4>;
184
185            clocks = <&dispcc_mdss_byte0_clk>,
186                     <&dispcc_mdss_byte0_intf_clk>,
187                     <&dispcc_mdss_pclk0_clk>,
188                     <&dispcc_mdss_esc0_clk>,
189                     <&dispcc_mdss_ahb_clk>,
190                     <&gcc_disp_hf_axi_clk>;
191            clock-names = "byte",
192                          "byte_intf",
193                          "pixel",
194                          "core",
195                          "iface",
196                          "bus";
197
198            assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
199                              <&dispcc_mdss_pclk0_clk_src>;
200            assigned-clock-parents = <&mdss_dsi0_phy 0>,
201                                     <&mdss_dsi0_phy 1>;
202
203            operating-points-v2 = <&dsi0_opp_table>;
204
205            phys = <&mdss_dsi0_phy>;
206
207            #address-cells = <1>;
208            #size-cells = <0>;
209
210            ports {
211                #address-cells = <1>;
212                #size-cells = <0>;
213
214                port@0 {
215                    reg = <0>;
216                    mdss_dsi0_in: endpoint {
217                        remote-endpoint = <&dpu_intf1_out>;
218                    };
219                };
220
221                port@1 {
222                    reg = <1>;
223                    mdss_dsi0_out: endpoint {
224                    };
225                };
226            };
227
228            dsi0_opp_table: opp-table {
229                compatible = "operating-points-v2";
230
231                opp-164000000 {
232                    opp-hz = /bits/ 64 <164000000>;
233                    required-opps = <&rpmhpd_opp_low_svs>;
234                };
235            };
236        };
237
238        mdss_dsi0_phy: phy@ae94400 {
239            compatible = "qcom,sm6150-dsi-phy-14nm";
240            reg = <0x0ae94400 0x100>,
241                  <0x0ae94500 0x300>,
242                  <0x0ae94800 0x188>;
243            reg-names = "dsi_phy",
244                        "dsi_phy_lane",
245                        "dsi_pll";
246
247            #clock-cells = <1>;
248            #phy-cells = <0>;
249
250            clocks = <&dispcc_mdss_ahb_clk>,
251                     <&rpmhcc RPMH_CXO_CLK>;
252            clock-names = "iface", "ref";
253        };
254    };
255...