qcom,sc8180x-dpu.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/msm/qcom,sc8180x-dpu.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SC8180X Display DPU
  8
  9maintainers:
 10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 11
 12$ref: /schemas/display/msm/dpu-common.yaml#
 13
 14properties:
 15  compatible:
 16    const: qcom,sc8180x-dpu
 17
 18  reg:
 19    items:
 20      - description: Address offset and size for mdp register set
 21      - description: Address offset and size for vbif register set
 22
 23  reg-names:
 24    items:
 25      - const: mdp
 26      - const: vbif
 27
 28  clocks:
 29    items:
 30      - description: Display AHB clock
 31      - description: Display HF AXI clock
 32      - description: Display core clock
 33      - description: Display vsync clock
 34      - description: Display rotator clock
 35      - description: Display LUT clock
 36
 37  clock-names:
 38    items:
 39      - const: iface
 40      - const: bus
 41      - const: core
 42      - const: vsync
 43      - const: rot
 44      - const: lut
 45
 46unevaluatedProperties: false
 47
 48examples:
 49  - |
 50    #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
 51    #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
 52    #include <dt-bindings/interrupt-controller/arm-gic.h>
 53    #include <dt-bindings/interconnect/qcom,sc8180x.h>
 54    #include <dt-bindings/power/qcom-rpmpd.h>
 55
 56    display-controller@ae01000 {
 57        compatible = "qcom,sc8180x-dpu";
 58        reg = <0x0ae01000 0x8f000>,
 59              <0x0aeb0000 0x2008>;
 60        reg-names = "mdp", "vbif";
 61
 62        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 63                 <&gcc GCC_DISP_HF_AXI_CLK>,
 64                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
 65                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
 66                 <&dispcc DISP_CC_MDSS_ROT_CLK>,
 67                 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
 68        clock-names = "iface",
 69                      "bus",
 70                      "core",
 71                      "vsync",
 72                      "rot",
 73                      "lut";
 74
 75        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 76        assigned-clock-rates = <19200000>;
 77
 78        operating-points-v2 = <&mdp_opp_table>;
 79        power-domains = <&rpmhpd SC8180X_MMCX>;
 80
 81        interrupt-parent = <&mdss>;
 82        interrupts = <0>;
 83
 84        ports {
 85            #address-cells = <1>;
 86            #size-cells = <0>;
 87
 88            port@0 {
 89                reg = <0>;
 90                endpoint {
 91                    remote-endpoint = <&dsi0_in>;
 92                };
 93            };
 94
 95            port@1 {
 96                reg = <1>;
 97                endpoint {
 98                    remote-endpoint = <&dsi1_in>;
 99                };
100            };
101        };
102    };
103...