qcom,sc7280-dpu.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Display DPU on SC7280
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Neil Armstrong <neil.armstrong@linaro.org>
 12  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 13  - Krishna Manikandan <quic_mkrishn@quicinc.com>
 14
 15$ref: /schemas/display/msm/dpu-common.yaml#
 16
 17properties:
 18  compatible:
 19    enum:
 20      - qcom,sar2130p-dpu
 21      - qcom,sc7280-dpu
 22      - qcom,sc8280xp-dpu
 23      - qcom,sm8350-dpu
 24      - qcom,sm8450-dpu
 25      - qcom,sm8550-dpu
 26
 27  reg:
 28    items:
 29      - description: Address offset and size for mdp register set
 30      - description: Address offset and size for vbif register set
 31
 32  reg-names:
 33    items:
 34      - const: mdp
 35      - const: vbif
 36
 37  clocks:
 38    items:
 39      - description: Display hf axi clock
 40      - description: Display sf axi clock
 41      - description: Display ahb clock
 42      - description: Display lut clock
 43      - description: Display core clock
 44      - description: Display vsync clock
 45
 46  clock-names:
 47    items:
 48      - const: bus
 49      - const: nrt_bus
 50      - const: iface
 51      - const: lut
 52      - const: core
 53      - const: vsync
 54
 55required:
 56  - compatible
 57  - reg
 58  - reg-names
 59  - clocks
 60  - clock-names
 61
 62unevaluatedProperties: false
 63
 64examples:
 65  - |
 66    #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
 67    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
 68    #include <dt-bindings/power/qcom-rpmpd.h>
 69
 70    display-controller@ae01000 {
 71        compatible = "qcom,sc7280-dpu";
 72        reg = <0x0ae01000 0x8f000>,
 73              <0x0aeb0000 0x2008>;
 74
 75        reg-names = "mdp", "vbif";
 76
 77        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
 78                 <&gcc GCC_DISP_SF_AXI_CLK>,
 79                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
 80                 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
 81                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
 82                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 83        clock-names = "bus",
 84                      "nrt_bus",
 85                      "iface",
 86                      "lut",
 87                      "core",
 88                      "vsync";
 89
 90        interrupt-parent = <&mdss>;
 91        interrupts = <0>;
 92        power-domains = <&rpmhpd SC7280_CX>;
 93        operating-points-v2 = <&mdp_opp_table>;
 94
 95        ports {
 96            #address-cells = <1>;
 97            #size-cells = <0>;
 98
 99            port@0 {
100                reg = <0>;
101                endpoint {
102                    remote-endpoint = <&dsi0_in>;
103                };
104            };
105
106            port@1 {
107                reg = <1>;
108                endpoint {
109                    remote-endpoint = <&edp_in>;
110                };
111            };
112        };
113    };
114...