qcom,qcs8300-mdss.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/msm/qcom,qcs8300-mdss.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Technologies, Inc. QCS8300 Display MDSS
  8
  9maintainers:
 10  - Yongxing Mou <yongxing.mou@oss.qualcomm.com>
 11
 12description:
 13  QCS8300 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
 14  DPU display controller, DP interfaces and EDP etc.
 15
 16$ref: /schemas/display/msm/mdss-common.yaml#
 17
 18properties:
 19  compatible:
 20    const: qcom,qcs8300-mdss
 21
 22  clocks:
 23    items:
 24      - description: Display AHB
 25      - description: Display hf AXI
 26      - description: Display core
 27
 28  iommus:
 29    maxItems: 1
 30
 31  interconnects:
 32    maxItems: 3
 33
 34  interconnect-names:
 35    maxItems: 3
 36
 37patternProperties:
 38  "^display-controller@[0-9a-f]+$":
 39    type: object
 40    additionalProperties: true
 41
 42    properties:
 43      compatible:
 44        contains:
 45          const: qcom,qcs8300-dpu
 46
 47  "^displayport-controller@[0-9a-f]+$":
 48    type: object
 49    additionalProperties: true
 50
 51    properties:
 52      compatible:
 53        contains:
 54          const: qcom,qcs8300-dp
 55
 56  "^phy@[0-9a-f]+$":
 57    type: object
 58    additionalProperties: true
 59    properties:
 60      compatible:
 61        contains:
 62          const: qcom,qcs8300-edp-phy
 63
 64required:
 65  - compatible
 66
 67unevaluatedProperties: false
 68
 69examples:
 70  - |
 71    #include <dt-bindings/interconnect/qcom,icc.h>
 72    #include <dt-bindings/interrupt-controller/arm-gic.h>
 73    #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
 74    #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
 75    #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
 76    #include <dt-bindings/power/qcom,rpmhpd.h>
 77    #include <dt-bindings/power/qcom-rpmpd.h>
 78
 79    mdss: display-subsystem@ae00000 {
 80        compatible = "qcom,qcs8300-mdss";
 81        reg = <0x0ae00000 0x1000>;
 82        reg-names = "mdss";
 83
 84        interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
 85                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
 86                        <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY
 87                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
 88                        <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
 89                         &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
 90        interconnect-names = "mdp0-mem",
 91                             "mdp1-mem",
 92                             "cpu-cfg";
 93
 94        resets = <&dispcc_core_bcr>;
 95        power-domains = <&dispcc_gdsc>;
 96
 97        clocks = <&dispcc_ahb_clk>,
 98                 <&gcc GCC_DISP_HF_AXI_CLK>,
 99                 <&dispcc_mdp_clk>;
100
101        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
102        interrupt-controller;
103        #interrupt-cells = <1>;
104
105        iommus = <&apps_smmu 0x1000 0x402>;
106
107        #address-cells = <1>;
108        #size-cells = <1>;
109        ranges;
110
111        display-controller@ae01000 {
112            compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu";
113            reg = <0x0ae01000 0x8f000>,
114                  <0x0aeb0000 0x2008>;
115            reg-names = "mdp", "vbif";
116
117            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
118                     <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
119                     <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
120                     <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
121                     <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
122            clock-names = "nrt_bus",
123                          "iface",
124                          "lut",
125                          "core",
126                          "vsync";
127
128            assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
129            assigned-clock-rates = <19200000>;
130            operating-points-v2 = <&mdp_opp_table>;
131            power-domains = <&rpmhpd RPMHPD_MMCX>;
132
133            interrupt-parent = <&mdss>;
134            interrupts = <0>;
135            ports {
136                #address-cells = <1>;
137                #size-cells = <0>;
138                port@0 {
139                    reg = <0>;
140
141                    dpu_intf0_out: endpoint {
142                         remote-endpoint = <&mdss_dp0_in>;
143                    };
144                };
145            };
146
147            mdp_opp_table: opp-table {
148                compatible = "operating-points-v2";
149
150                opp-375000000 {
151                    opp-hz = /bits/ 64 <375000000>;
152                    required-opps = <&rpmhpd_opp_svs_l1>;
153                };
154
155                opp-500000000 {
156                    opp-hz = /bits/ 64 <500000000>;
157                    required-opps = <&rpmhpd_opp_nom>;
158                };
159
160                opp-575000000 {
161                    opp-hz = /bits/ 64 <575000000>;
162                    required-opps = <&rpmhpd_opp_turbo>;
163                };
164
165                opp-650000000 {
166                    opp-hz = /bits/ 64 <650000000>;
167                    required-opps = <&rpmhpd_opp_turbo_l1>;
168                };
169            };
170        };
171
172        mdss_dp0_phy: phy@aec2a00 {
173            compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
174
175            reg = <0x0aec2a00 0x200>,
176                  <0x0aec2200 0xd0>,
177                  <0x0aec2600 0xd0>,
178                  <0x0aec2000 0x1c8>;
179
180            clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
181                     <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
182            clock-names = "aux",
183                          "cfg_ahb";
184
185            #clock-cells = <1>;
186            #phy-cells = <0>;
187
188            vdda-phy-supply = <&vreg_l1c>;
189            vdda-pll-supply = <&vreg_l4a>;
190        };
191
192        displayport-controller@af54000 {
193            compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp";
194
195            pinctrl-0 = <&dp_hot_plug_det>;
196            pinctrl-names = "default";
197
198            reg = <0xaf54000 0x104>,
199                  <0xaf54200 0x0c0>,
200                  <0xaf55000 0x770>,
201                  <0xaf56000 0x09c>,
202                  <0xaf57000 0x09c>,
203                  <0xaf58000 0x09c>,
204                  <0xaf59000 0x09c>,
205                  <0xaf5a000 0x23c>,
206                  <0xaf5b000 0x23c>;
207
208            interrupt-parent = <&mdss>;
209            interrupts = <12>;
210            clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
211                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
212                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
213                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
214                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
215                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
216                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
217                     <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
218            clock-names = "core_iface",
219                          "core_aux",
220                          "ctrl_link",
221                          "ctrl_link_iface",
222                          "stream_pixel",
223                          "stream_1_pixel",
224                          "stream_2_pixel",
225                          "stream_3_pixel";
226            assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
227                              <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
228                              <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
229                              <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
230                              <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
231            assigned-clock-parents = <&mdss_dp0_phy 0>,
232                                     <&mdss_dp0_phy 1>,
233                                     <&mdss_dp0_phy 1>,
234                                     <&mdss_dp0_phy 1>;
235            phys = <&mdss_dp0_phy>;
236            phy-names = "dp";
237            operating-points-v2 = <&dp_opp_table>;
238            power-domains = <&rpmhpd RPMHPD_MMCX>;
239
240            #sound-dai-cells = <0>;
241
242            ports {
243                #address-cells = <1>;
244                #size-cells = <0>;
245
246                port@0 {
247                    reg = <0>;
248
249                    mdss_dp0_in: endpoint {
250                        remote-endpoint = <&dpu_intf0_out>;
251                    };
252                };
253
254                port@1 {
255                   reg = <1>;
256
257                   mdss_dp_out: endpoint { };
258                };
259            };
260
261            dp_opp_table: opp-table {
262                compatible = "operating-points-v2";
263
264                opp-160000000 {
265                    opp-hz = /bits/ 64 <160000000>;
266                    required-opps = <&rpmhpd_opp_low_svs>;
267                };
268
269                opp-270000000 {
270                    opp-hz = /bits/ 64 <270000000>;
271                    required-opps = <&rpmhpd_opp_svs>;
272                };
273
274                opp-540000000 {
275                    opp-hz = /bits/ 64 <540000000>;
276                    required-opps = <&rpmhpd_opp_svs_l1>;
277                };
278
279                opp-810000000 {
280                    opp-hz = /bits/ 64 <810000000>;
281                    required-opps = <&rpmhpd_opp_nom>;
282                };
283            };
284        };
285    };
286...