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dsi-controller-main.yaml
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linux-6.19.14/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,msm8226-dsi-ctrl 19 - qcom,msm8916-dsi-ctrl 20 - qcom,msm8953-dsi-ctrl 21 - qcom,msm8974-dsi-ctrl 22 - qcom,msm8976-dsi-ctrl 23 - qcom,msm8996-dsi-ctrl 24 - qcom,msm8998-dsi-ctrl 25 - qcom,qcm2290-dsi-ctrl 26 - qcom,sa8775p-dsi-ctrl 27 - qcom,sar2130p-dsi-ctrl 28 - qcom,sc7180-dsi-ctrl 29 - qcom,sc7280-dsi-ctrl 30 - qcom,sc8180x-dsi-ctrl 31 - qcom,sdm660-dsi-ctrl 32 - qcom,sdm670-dsi-ctrl 33 - qcom,sdm845-dsi-ctrl 34 - qcom,sm6115-dsi-ctrl 35 - qcom,sm6125-dsi-ctrl 36 - qcom,sm6150-dsi-ctrl 37 - qcom,sm6350-dsi-ctrl 38 - qcom,sm6375-dsi-ctrl 39 - qcom,sm7150-dsi-ctrl 40 - qcom,sm8150-dsi-ctrl 41 - qcom,sm8250-dsi-ctrl 42 - qcom,sm8350-dsi-ctrl 43 - qcom,sm8450-dsi-ctrl 44 - qcom,sm8550-dsi-ctrl 45 - qcom,sm8650-dsi-ctrl 46 - qcom,sm8750-dsi-ctrl 47 - const: qcom,mdss-dsi-ctrl 48 - enum: 49 - qcom,dsi-ctrl-6g-qcm2290 50 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible 51 deprecated: true 52 53 reg: 54 maxItems: 1 55 56 reg-names: 57 const: dsi_ctrl 58 59 interrupts: 60 maxItems: 1 61 62 clocks: 63 description: | 64 Several clocks are used, depending on the variant. Typical ones are:: 65 - bus:: Display AHB clock. 66 - byte:: Display byte clock. 67 - byte_intf:: Display byte interface clock. 68 - core:: Display core clock. 69 - core_mss:: Core MultiMedia SubSystem clock. 70 - iface:: Display AXI clock. 71 - mdp_core:: MDP Core clock. 72 - mnoc:: MNOC clock 73 - pixel:: Display pixel clock. 74 minItems: 3 75 maxItems: 12 76 77 clock-names: 78 minItems: 3 79 maxItems: 12 80 81 phys: 82 maxItems: 1 83 84 phy-names: 85 deprecated: true 86 const: dsi 87 88 syscon-sfpb: 89 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 90 $ref: /schemas/types.yaml#/definitions/phandle 91 92 qcom,dual-dsi-mode: 93 type: boolean 94 description: | 95 Indicates if the DSI controller is driving a panel which needs 96 2 DSI links. 97 98 qcom,master-dsi: 99 type: boolean 100 description: | 101 Indicates if the DSI controller is the master DSI controller when 102 qcom,dual-dsi-mode enabled. 103 104 qcom,sync-dual-dsi: 105 type: boolean 106 description: | 107 Indicates if the DSI controller needs to sync the other DSI controller 108 with MIPI DCS commands when qcom,dual-dsi-mode enabled. 109 110 assigned-clocks: 111 minItems: 2 112 maxItems: 4 113 description: | 114 For DSI on SM8650 and older: parents of "byte" and "pixel" for the given 115 platform. 116 For DSIv2 platforms this should contain "byte", "esc", "src" and 117 "pixel_src" clocks. 118 119 assigned-clock-parents: 120 minItems: 2 121 maxItems: 4 122 description: | 123 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 124 125 power-domains: 126 maxItems: 1 127 128 operating-points-v2: true 129 130 opp-table: 131 type: object 132 133 ports: 134 $ref: /schemas/graph.yaml#/properties/ports 135 description: | 136 Contains DSI controller input and output ports as children, each 137 containing one endpoint subnode. 138 139 properties: 140 port@0: 141 $ref: /schemas/graph.yaml#/$defs/port-base 142 unevaluatedProperties: false 143 description: | 144 Input endpoints of the controller. 145 properties: 146 endpoint: 147 $ref: /schemas/media/video-interfaces.yaml# 148 unevaluatedProperties: false 149 properties: 150 data-lanes: 151 maxItems: 4 152 minItems: 1 153 items: 154 enum: [ 0, 1, 2, 3 ] 155 156 port@1: 157 $ref: /schemas/graph.yaml#/$defs/port-base 158 unevaluatedProperties: false 159 description: | 160 Output endpoints of the controller. 161 properties: 162 endpoint: 163 $ref: /schemas/media/video-interfaces.yaml# 164 unevaluatedProperties: false 165 properties: 166 data-lanes: 167 maxItems: 4 168 minItems: 1 169 items: 170 enum: [ 0, 1, 2, 3 ] 171 172 qcom,te-source: 173 $ref: /schemas/types.yaml#/definitions/string 174 description: 175 Specifies the source of vsync signal from the panel used for 176 tearing elimination. 177 default: mdp_vsync_p 178 enum: 179 - mdp_vsync_p 180 - mdp_vsync_s 181 - mdp_vsync_e 182 - timer0 183 - timer1 184 - timer2 185 - timer3 186 - timer4 187 188 required: 189 - port@0 190 - port@1 191 192 avdd-supply: 193 description: 194 Phandle to vdd regulator device node 195 196 refgen-supply: 197 description: 198 Phandle to REFGEN regulator device node 199 200 vcca-supply: 201 description: 202 Phandle to vdd regulator device node 203 204 vdd-supply: 205 description: 206 VDD regulator 207 208 vddio-supply: 209 description: 210 VDD-IO regulator 211 212 vdda-supply: 213 description: 214 VDDA regulator 215 216required: 217 - compatible 218 - reg 219 - reg-names 220 - interrupts 221 - clocks 222 - clock-names 223 - phys 224 - ports 225 226allOf: 227 - $ref: ../dsi-controller.yaml# 228 - if: 229 properties: 230 compatible: 231 contains: 232 enum: 233 - qcom,apq8064-dsi-ctrl 234 then: 235 properties: 236 clocks: 237 minItems: 7 238 maxItems: 7 239 clock-names: 240 items: 241 - const: iface 242 - const: bus 243 - const: core_mmss 244 - const: src 245 - const: byte 246 - const: pixel 247 - const: core 248 required: 249 - assigned-clocks 250 - assigned-clock-parents 251 252 - if: 253 properties: 254 compatible: 255 contains: 256 enum: 257 - qcom,msm8916-dsi-ctrl 258 - qcom,msm8953-dsi-ctrl 259 - qcom,msm8976-dsi-ctrl 260 then: 261 properties: 262 clocks: 263 minItems: 6 264 maxItems: 6 265 clock-names: 266 items: 267 - const: mdp_core 268 - const: iface 269 - const: bus 270 - const: byte 271 - const: pixel 272 - const: core 273 required: 274 - assigned-clocks 275 - assigned-clock-parents 276 277 - if: 278 properties: 279 compatible: 280 contains: 281 enum: 282 - qcom,msm8226-dsi-ctrl 283 - qcom,msm8974-dsi-ctrl 284 then: 285 properties: 286 clocks: 287 minItems: 7 288 maxItems: 7 289 clock-names: 290 items: 291 - const: mdp_core 292 - const: iface 293 - const: bus 294 - const: byte 295 - const: pixel 296 - const: core 297 - const: core_mmss 298 required: 299 - assigned-clocks 300 - assigned-clock-parents 301 302 - if: 303 properties: 304 compatible: 305 contains: 306 enum: 307 - qcom,msm8996-dsi-ctrl 308 then: 309 properties: 310 clocks: 311 minItems: 7 312 maxItems: 7 313 clock-names: 314 items: 315 - const: mdp_core 316 - const: byte 317 - const: iface 318 - const: bus 319 - const: core_mmss 320 - const: pixel 321 - const: core 322 required: 323 - assigned-clocks 324 - assigned-clock-parents 325 326 - if: 327 properties: 328 compatible: 329 contains: 330 enum: 331 - qcom,msm8998-dsi-ctrl 332 - qcom,sa8775p-dsi-ctrl 333 - qcom,sar2130p-dsi-ctrl 334 - qcom,sc7180-dsi-ctrl 335 - qcom,sc7280-dsi-ctrl 336 - qcom,sc8180x-dsi-ctrl 337 - qcom,sdm845-dsi-ctrl 338 - qcom,sm6115-dsi-ctrl 339 - qcom,sm6125-dsi-ctrl 340 - qcom,sm6350-dsi-ctrl 341 - qcom,sm6375-dsi-ctrl 342 - qcom,sm6150-dsi-ctrl 343 - qcom,sm7150-dsi-ctrl 344 - qcom,sm8150-dsi-ctrl 345 - qcom,sm8250-dsi-ctrl 346 - qcom,sm8350-dsi-ctrl 347 - qcom,sm8450-dsi-ctrl 348 - qcom,sm8550-dsi-ctrl 349 - qcom,sm8650-dsi-ctrl 350 then: 351 properties: 352 clocks: 353 minItems: 6 354 maxItems: 6 355 clock-names: 356 items: 357 - const: byte 358 - const: byte_intf 359 - const: pixel 360 - const: core 361 - const: iface 362 - const: bus 363 required: 364 - assigned-clocks 365 - assigned-clock-parents 366 367 - if: 368 properties: 369 compatible: 370 contains: 371 enum: 372 - qcom,sm8750-dsi-ctrl 373 then: 374 properties: 375 clocks: 376 minItems: 12 377 maxItems: 12 378 clock-names: 379 items: 380 - const: byte 381 - const: byte_intf 382 - const: pixel 383 - const: core 384 - const: iface 385 - const: bus 386 - const: dsi_pll_pixel 387 - const: dsi_pll_byte 388 - const: esync 389 - const: osc 390 - const: byte_src 391 - const: pixel_src 392 393 - if: 394 properties: 395 compatible: 396 contains: 397 enum: 398 - qcom,sdm660-dsi-ctrl 399 then: 400 properties: 401 clocks: 402 minItems: 9 403 maxItems: 9 404 clock-names: 405 items: 406 - const: mdp_core 407 - const: byte 408 - const: byte_intf 409 - const: mnoc 410 - const: iface 411 - const: bus 412 - const: core_mmss 413 - const: pixel 414 - const: core 415 required: 416 - assigned-clocks 417 - assigned-clock-parents 418 419unevaluatedProperties: false 420 421examples: 422 - | 423 #include <dt-bindings/interrupt-controller/arm-gic.h> 424 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 425 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 426 #include <dt-bindings/power/qcom-rpmpd.h> 427 428 dsi@ae94000 { 429 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 430 reg = <0x0ae94000 0x400>; 431 reg-names = "dsi_ctrl"; 432 433 #address-cells = <1>; 434 #size-cells = <0>; 435 436 interrupt-parent = <&mdss>; 437 interrupts = <4>; 438 439 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 440 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 441 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 442 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 443 <&dispcc DISP_CC_MDSS_AHB_CLK>, 444 <&dispcc DISP_CC_MDSS_AXI_CLK>; 445 clock-names = "byte", 446 "byte_intf", 447 "pixel", 448 "core", 449 "iface", 450 "bus"; 451 452 phys = <&dsi0_phy>; 453 phy-names = "dsi"; 454 455 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 456 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 457 458 power-domains = <&rpmhpd SC7180_CX>; 459 operating-points-v2 = <&dsi_opp_table>; 460 461 ports { 462 #address-cells = <1>; 463 #size-cells = <0>; 464 465 port@0 { 466 reg = <0>; 467 endpoint { 468 remote-endpoint = <&dpu_intf1_out>; 469 }; 470 }; 471 472 port@1 { 473 reg = <1>; 474 endpoint { 475 remote-endpoint = <&sn65dsi86_in>; 476 data-lanes = <0 1 2 3>; 477 qcom,te-source = "mdp_vsync_e"; 478 }; 479 }; 480 }; 481 }; 482...
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