mediatek,rdma.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Mediatek Read Direct Memory Access
  8
  9maintainers:
 10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
 11  - Philipp Zabel <p.zabel@pengutronix.de>
 12
 13description: |
 14  Mediatek Read Direct Memory Access(RDMA) component used to read the
 15  data into DMA. It provides real time data to the back-end panel
 16  driver, such as DSI, DPI and DP_INTF.
 17  It contains one line buffer to store the sufficient pixel data.
 18  RDMA device node must be siblings to the central MMSYS_CONFIG node.
 19  For a description of the MMSYS_CONFIG binding, see
 20  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
 21  for details.
 22
 23properties:
 24  compatible:
 25    oneOf:
 26      - enum:
 27          - mediatek,mt2701-disp-rdma
 28          - mediatek,mt8173-disp-rdma
 29          - mediatek,mt8183-disp-rdma
 30          - mediatek,mt8195-disp-rdma
 31      - items:
 32          - enum:
 33              - mediatek,mt8188-disp-rdma
 34          - const: mediatek,mt8195-disp-rdma
 35      - items:
 36          - enum:
 37              - mediatek,mt7623-disp-rdma
 38              - mediatek,mt2712-disp-rdma
 39          - const: mediatek,mt2701-disp-rdma
 40      - items:
 41          - enum:
 42              - mediatek,mt6795-disp-rdma
 43          - const: mediatek,mt8173-disp-rdma
 44      - items:
 45          - enum:
 46              - mediatek,mt8186-disp-rdma
 47              - mediatek,mt8192-disp-rdma
 48              - mediatek,mt8365-disp-rdma
 49          - const: mediatek,mt8183-disp-rdma
 50
 51  reg:
 52    maxItems: 1
 53
 54  interrupts:
 55    maxItems: 1
 56
 57  power-domains:
 58    description: A phandle and PM domain specifier as defined by bindings of
 59      the power controller specified by phandle. See
 60      Documentation/devicetree/bindings/power/power-domain.yaml for details.
 61
 62  clocks:
 63    items:
 64      - description: RDMA Clock
 65
 66  iommus:
 67    description:
 68      This property should point to the respective IOMMU block with master port as argument,
 69      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
 70
 71  mediatek,rdma-fifo-size:
 72    description:
 73      rdma fifo size may be different even in same SOC, add this property to the
 74      corresponding rdma.
 75      The value below is the Max value which defined in hardware data sheet
 76      mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
 77      mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
 78      mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
 79    $ref: /schemas/types.yaml#/definitions/uint32
 80    enum: [8192, 5120, 2048]
 81
 82  mediatek,gce-client-reg:
 83    description: The register of client driver can be configured by gce with
 84      4 arguments defined in this property, such as phandle of gce, subsys id,
 85      register offset and size. Each GCE subsys id is mapping to a client
 86      defined in the header include/dt-bindings/gce/<chip>-gce.h.
 87    $ref: /schemas/types.yaml#/definitions/phandle-array
 88    maxItems: 1
 89
 90  ports:
 91    $ref: /schemas/graph.yaml#/properties/ports
 92    description:
 93      Input and output ports can have multiple endpoints, each of those
 94      connects to either the primary, secondary, etc, display pipeline.
 95
 96    properties:
 97      port@0:
 98        $ref: /schemas/graph.yaml#/properties/port
 99        description: RDMA input port, usually from MMSYS, OD or OVL
100
101      port@1:
102        $ref: /schemas/graph.yaml#/properties/port
103        description:
104          RDMA output to the input of the next desired component in the
105          display pipeline, for example one of the available COLOR, DPI,
106          DSI, MERGE or UFOE blocks.
107
108    required:
109      - port@0
110      - port@1
111
112required:
113  - compatible
114  - reg
115  - interrupts
116  - power-domains
117  - clocks
118  - iommus
119
120additionalProperties: false
121
122examples:
123  - |
124    #include <dt-bindings/interrupt-controller/arm-gic.h>
125    #include <dt-bindings/clock/mt8173-clk.h>
126    #include <dt-bindings/power/mt8173-power.h>
127    #include <dt-bindings/gce/mt8173-gce.h>
128    #include <dt-bindings/memory/mt8173-larb-port.h>
129
130    soc {
131        #address-cells = <2>;
132        #size-cells = <2>;
133
134        rdma0: rdma@1400e000 {
135            compatible = "mediatek,mt8173-disp-rdma";
136            reg = <0 0x1400e000 0 0x1000>;
137            interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
138            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
139            clocks = <&mmsys CLK_MM_DISP_RDMA0>;
140            iommus = <&iommu M4U_PORT_DISP_RDMA0>;
141            mediatek,rdma-fifo-size = <8192>;
142            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
143        };
144    };