mediatek,ovl.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Mediatek display overlay
  8
  9maintainers:
 10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
 11  - Philipp Zabel <p.zabel@pengutronix.de>
 12
 13description: |
 14  Mediatek display overlay, namely OVL, can do alpha blending from
 15  the memory.
 16  OVL device node must be siblings to the central MMSYS_CONFIG node.
 17  For a description of the MMSYS_CONFIG binding, see
 18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
 19  for details.
 20
 21properties:
 22  compatible:
 23    oneOf:
 24      - enum:
 25          - mediatek,mt2701-disp-ovl
 26          - mediatek,mt8173-disp-ovl
 27          - mediatek,mt8183-disp-ovl
 28          - mediatek,mt8192-disp-ovl
 29          - mediatek,mt8195-disp-ovl
 30          - mediatek,mt8195-mdp3-ovl
 31      - items:
 32          - enum:
 33              - mediatek,mt7623-disp-ovl
 34              - mediatek,mt2712-disp-ovl
 35          - const: mediatek,mt2701-disp-ovl
 36      - items:
 37          - enum:
 38              - mediatek,mt6795-disp-ovl
 39          - const: mediatek,mt8173-disp-ovl
 40      - items:
 41          - enum:
 42              - mediatek,mt8186-disp-ovl
 43              - mediatek,mt8365-disp-ovl
 44          - const: mediatek,mt8192-disp-ovl
 45      - items:
 46          - const: mediatek,mt8188-disp-ovl
 47          - const: mediatek,mt8195-disp-ovl
 48      - items:
 49          - const: mediatek,mt8188-mdp3-ovl
 50          - const: mediatek,mt8195-mdp3-ovl
 51
 52  reg:
 53    maxItems: 1
 54
 55  interrupts:
 56    maxItems: 1
 57
 58  power-domains:
 59    description: A phandle and PM domain specifier as defined by bindings of
 60      the power controller specified by phandle. See
 61      Documentation/devicetree/bindings/power/power-domain.yaml for details.
 62
 63  clocks:
 64    items:
 65      - description: OVL Clock
 66
 67  iommus:
 68    description:
 69      This property should point to the respective IOMMU block with master port as argument,
 70      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
 71
 72  mediatek,gce-client-reg:
 73    description: The register of client driver can be configured by gce with
 74      4 arguments defined in this property, such as phandle of gce, subsys id,
 75      register offset and size. Each GCE subsys id is mapping to a client
 76      defined in the header include/dt-bindings/gce/<chip>-gce.h.
 77    $ref: /schemas/types.yaml#/definitions/phandle-array
 78    maxItems: 1
 79
 80  ports:
 81    $ref: /schemas/graph.yaml#/properties/ports
 82    description:
 83      Input and output ports can have multiple endpoints, each of those
 84      connects to either the primary, secondary, etc, display pipeline.
 85
 86    properties:
 87      port@0:
 88        $ref: /schemas/graph.yaml#/properties/port
 89        description: OVL input port from MMSYS or one of multiple VDOSYS
 90
 91      port@1:
 92        $ref: /schemas/graph.yaml#/properties/port
 93        description:
 94          OVL output to the input of the next desired component in the
 95          display pipeline, for example one of the available COLOR, RDMA
 96          or WDMA blocks.
 97
 98    required:
 99      - port@0
100      - port@1
101
102required:
103  - compatible
104  - reg
105  - interrupts
106  - power-domains
107  - clocks
108  - iommus
109
110additionalProperties: false
111
112examples:
113  - |
114    #include <dt-bindings/interrupt-controller/arm-gic.h>
115    #include <dt-bindings/clock/mt8173-clk.h>
116    #include <dt-bindings/power/mt8173-power.h>
117    #include <dt-bindings/gce/mt8173-gce.h>
118    #include <dt-bindings/memory/mt8173-larb-port.h>
119
120    soc {
121        #address-cells = <2>;
122        #size-cells = <2>;
123
124        ovl0: ovl@1400c000 {
125            compatible = "mediatek,mt8173-disp-ovl";
126            reg = <0 0x1400c000 0 0x1000>;
127            interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
128            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
129            clocks = <&mmsys CLK_MM_DISP_OVL0>;
130            iommus = <&iommu M4U_PORT_DISP_OVL0>;
131            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
132        };
133    };