mediatek,merge.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Mediatek display merge
  8
  9maintainers:
 10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
 11  - Philipp Zabel <p.zabel@pengutronix.de>
 12
 13description: |
 14  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
 15  inputs into one side-by-side output.
 16  MERGE device node must be siblings to the central MMSYS_CONFIG node.
 17  For a description of the MMSYS_CONFIG binding, see
 18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
 19  for details.
 20
 21properties:
 22  compatible:
 23    oneOf:
 24      - enum:
 25          - mediatek,mt8173-disp-merge
 26          - mediatek,mt8195-disp-merge
 27          - mediatek,mt8195-mdp3-merge
 28      - items:
 29          - enum:
 30              - mediatek,mt8188-mdp3-merge
 31          - const: mediatek,mt8195-mdp3-merge
 32      - items:
 33          - const: mediatek,mt6795-disp-merge
 34          - const: mediatek,mt8173-disp-merge
 35      - items:
 36          - const: mediatek,mt8188-disp-merge
 37          - const: mediatek,mt8195-disp-merge
 38
 39  reg:
 40    maxItems: 1
 41
 42  interrupts:
 43    maxItems: 1
 44
 45  power-domains:
 46    description: A phandle and PM domain specifier as defined by bindings of
 47      the power controller specified by phandle. See
 48      Documentation/devicetree/bindings/power/power-domain.yaml for details.
 49
 50  clocks:
 51    minItems: 1
 52    maxItems: 2
 53
 54  clock-names:
 55    oneOf:
 56      - items:
 57          - const: merge
 58      - items:
 59          - const: merge
 60          - const: merge_async
 61
 62  mediatek,merge-fifo-en:
 63    description:
 64      The setting of merge fifo is mainly provided for the display latency
 65      buffer to ensure that the back-end panel display data will not be
 66      underrun, a little more data is needed in the fifo.
 67      According to the merge fifo settings, when the water level is detected
 68      to be insufficient, it will trigger RDMA sending ultra and preulra
 69      command to SMI to speed up the data rate.
 70    type: boolean
 71
 72  mediatek,merge-mute:
 73    description: Support mute function. Mute the content of merge output.
 74    type: boolean
 75
 76  mediatek,gce-client-reg:
 77    description: The register of client driver can be configured by gce with
 78      4 arguments defined in this property, such as phandle of gce, subsys id,
 79      register offset and size. Each GCE subsys id is mapping to a client
 80      defined in the header include/dt-bindings/gce/<chip>-gce.h.
 81    $ref: /schemas/types.yaml#/definitions/phandle-array
 82    maxItems: 1
 83
 84  ports:
 85    $ref: /schemas/graph.yaml#/properties/ports
 86    description:
 87      Input and output ports can have multiple endpoints, each of those
 88      connects to either the primary, secondary, etc, display pipeline.
 89
 90    properties:
 91      port@0:
 92        $ref: /schemas/graph.yaml#/properties/port
 93        description:
 94          MERGE input port, usually from DITHER, DPI, DSC, DSI, MDP_RDMA,
 95          ETHDR or even from a different MERGE block
 96
 97      port@1:
 98        $ref: /schemas/graph.yaml#/properties/port
 99        description:
100          MERGE output to a DSC, DPI, DP_INTF, DSI, ETHDR, Write DMA, or
101          a different MERGE block, or others.
102
103    required:
104      - port@0
105      - port@1
106
107  resets:
108    description: reset controller
109      See Documentation/devicetree/bindings/reset/reset.txt for details.
110    maxItems: 1
111
112required:
113  - compatible
114  - reg
115  - power-domains
116  - clocks
117
118additionalProperties: false
119
120examples:
121  - |
122    #include <dt-bindings/interrupt-controller/arm-gic.h>
123    #include <dt-bindings/clock/mt8173-clk.h>
124    #include <dt-bindings/power/mt8173-power.h>
125
126    soc {
127        #address-cells = <2>;
128        #size-cells = <2>;
129
130        merge@14017000 {
131            compatible = "mediatek,mt8173-disp-merge";
132            reg = <0 0x14017000 0 0x1000>;
133            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
134            clocks = <&mmsys CLK_MM_DISP_MERGE>;
135            clock-names = "merge";
136        };
137    };