mediatek,ethdr.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: MediaTek Ethdr Device
  8
  9maintainers:
 10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
 11  - Philipp Zabel <p.zabel@pengutronix.de>
 12
 13description:
 14  ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and is
 15  designed for HDR video and graphics conversion in the external display path.
 16  It handles multiple HDR input types and performs tone mapping, color
 17  space/color format conversion, and then combine different layers,
 18  output the required HDR or SDR signal to the subsequent display path.
 19  This engine is composed of two video frontends, two graphic frontends,
 20  one video backend and a mixer. ETHDR has two DMA function blocks, DS and ADL.
 21  These two function blocks read the pre-programmed registers from DRAM and
 22  set them to HW in the v-blanking period.
 23
 24properties:
 25  compatible:
 26    oneOf:
 27      - const: mediatek,mt8195-disp-ethdr
 28      - items:
 29          - const: mediatek,mt8188-disp-ethdr
 30          - const: mediatek,mt8195-disp-ethdr
 31
 32  reg:
 33    maxItems: 7
 34
 35  reg-names:
 36    items:
 37      - const: mixer
 38      - const: vdo_fe0
 39      - const: vdo_fe1
 40      - const: gfx_fe0
 41      - const: gfx_fe1
 42      - const: vdo_be
 43      - const: adl_ds
 44
 45  interrupts:
 46    maxItems: 1
 47
 48  iommus:
 49    minItems: 1
 50    maxItems: 2
 51
 52  clocks:
 53    items:
 54      - description: mixer clock
 55      - description: video frontend 0 clock
 56      - description: video frontend 1 clock
 57      - description: graphic frontend 0 clock
 58      - description: graphic frontend 1 clock
 59      - description: video backend clock
 60      - description: autodownload and menuload clock
 61      - description: video frontend 0 async clock
 62      - description: video frontend 1 async clock
 63      - description: graphic frontend 0 async clock
 64      - description: graphic frontend 1 async clock
 65      - description: video backend async clock
 66      - description: ethdr top clock
 67
 68  clock-names:
 69    items:
 70      - const: mixer
 71      - const: vdo_fe0
 72      - const: vdo_fe1
 73      - const: gfx_fe0
 74      - const: gfx_fe1
 75      - const: vdo_be
 76      - const: adl_ds
 77      - const: vdo_fe0_async
 78      - const: vdo_fe1_async
 79      - const: gfx_fe0_async
 80      - const: gfx_fe1_async
 81      - const: vdo_be_async
 82      - const: ethdr_top
 83
 84  power-domains:
 85    maxItems: 1
 86
 87  resets:
 88    items:
 89      - description: video frontend 0 async reset
 90      - description: video frontend 1 async reset
 91      - description: graphic frontend 0 async reset
 92      - description: graphic frontend 1 async reset
 93      - description: video backend async reset
 94
 95  reset-names:
 96    items:
 97      - const: vdo_fe0_async
 98      - const: vdo_fe1_async
 99      - const: gfx_fe0_async
100      - const: gfx_fe1_async
101      - const: vdo_be_async
102
103  mediatek,gce-client-reg:
104    $ref: /schemas/types.yaml#/definitions/phandle-array
105    minItems: 1
106    maxItems: 7
107    description: The register of display function block to be set by gce.
108      There are 4 arguments in this property, gce node, subsys id, offset and
109      register size. The subsys id is defined in the gce header of each chips
110      include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
111      function block.
112
113  ports:
114    $ref: /schemas/graph.yaml#/properties/ports
115    description:
116      Input and output ports can have multiple endpoints, each of those
117      connects to either the primary, secondary, etc, display pipeline.
118
119    properties:
120      port@0:
121        $ref: /schemas/graph.yaml#/properties/port
122        description: ETHDR input, usually from one of the MERGE blocks.
123
124      port@1:
125        $ref: /schemas/graph.yaml#/properties/port
126        description:
127          ETHDR output to the input of the next desired component in the
128          display pipeline, for example one of the available MERGE blocks,
129          or others.
130
131    required:
132      - port@0
133      - port@1
134
135required:
136  - compatible
137  - reg
138  - clocks
139  - clock-names
140  - interrupts
141  - power-domains
142  - resets
143  - mediatek,gce-client-reg
144
145additionalProperties: false
146
147examples:
148  - |
149    #include <dt-bindings/interrupt-controller/arm-gic.h>
150    #include <dt-bindings/clock/mt8195-clk.h>
151    #include <dt-bindings/gce/mt8195-gce.h>
152    #include <dt-bindings/memory/mt8195-memory-port.h>
153    #include <dt-bindings/power/mt8195-power.h>
154    #include <dt-bindings/reset/mt8195-resets.h>
155
156    soc {
157        #address-cells = <2>;
158        #size-cells = <2>;
159
160        hdr-engine@1c114000 {
161                compatible = "mediatek,mt8195-disp-ethdr";
162                reg = <0 0x1c114000 0 0x1000>,
163                      <0 0x1c115000 0 0x1000>,
164                      <0 0x1c117000 0 0x1000>,
165                      <0 0x1c119000 0 0x1000>,
166                      <0 0x1c11a000 0 0x1000>,
167                      <0 0x1c11b000 0 0x1000>,
168                      <0 0x1c11c000 0 0x1000>;
169                reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
170                            "vdo_be", "adl_ds";
171                mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
172                                          <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
173                                          <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
174                                          <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
175                                          <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
176                                          <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
177                                          <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
178                clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
179                         <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
180                         <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
181                         <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
182                         <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
183                         <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
184                         <&vdosys1 CLK_VDO1_26M_SLOW>,
185                         <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
186                         <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
187                         <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
188                         <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
189                         <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
190                         <&topckgen CLK_TOP_ETHDR>;
191                clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
192                              "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
193                              "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
194                              "ethdr_top";
195                power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
196                iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
197                         <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
198                interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
199                resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
200                         <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
201                         <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
202                         <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
203                         <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
204                reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
205                              "gfx_fe1_async", "vdo_be_async";
206        };
207    };
208...