mediatek,dpi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: MediaTek DPI and DP_INTF Controller
  8
  9maintainers:
 10  - CK Hu <ck.hu@mediatek.com>
 11  - Jitao shi <jitao.shi@mediatek.com>
 12
 13description: |
 14  The MediaTek DPI and DP_INTF function blocks are a sink of the display
 15  subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
 16  parallel output bus.
 17
 18properties:
 19  compatible:
 20    oneOf:
 21      - enum:
 22          - mediatek,mt2701-dpi
 23          - mediatek,mt7623-dpi
 24          - mediatek,mt8173-dpi
 25          - mediatek,mt8183-dpi
 26          - mediatek,mt8186-dpi
 27          - mediatek,mt8188-dp-intf
 28          - mediatek,mt8192-dpi
 29          - mediatek,mt8195-dp-intf
 30          - mediatek,mt8195-dpi
 31      - items:
 32          - enum:
 33              - mediatek,mt6795-dpi
 34          - const: mediatek,mt8183-dpi
 35      - items:
 36          - enum:
 37              - mediatek,mt8365-dpi
 38          - const: mediatek,mt8192-dpi
 39      - items:
 40          - enum:
 41              - mediatek,mt8188-dpi
 42          - const: mediatek,mt8195-dpi
 43
 44  reg:
 45    maxItems: 1
 46
 47  interrupts:
 48    maxItems: 1
 49
 50  clocks:
 51    items:
 52      - description: Pixel Clock
 53      - description: Engine Clock
 54      - description: DPI PLL
 55
 56  clock-names:
 57    items:
 58      - const: pixel
 59      - const: engine
 60      - const: pll
 61
 62  pinctrl-0: true
 63  pinctrl-1: true
 64
 65  pinctrl-names:
 66    items:
 67      - const: default
 68      - const: sleep
 69
 70  power-domains:
 71    description: |
 72      The MediaTek DPI module is typically associated with one of the
 73      following multimedia power domains:
 74        POWER_DOMAIN_DISPLAY
 75        POWER_DOMAIN_VDOSYS
 76        POWER_DOMAIN_MM
 77      The specific power domain used varies depending on the SoC design.
 78
 79      It is recommended to explicitly add the appropriate power domain
 80      property to the DPI node in the device tree.
 81    maxItems: 1
 82
 83  port:
 84    $ref: /schemas/graph.yaml#/properties/port
 85    description:
 86      Output port node. This port should be connected to the input port of an
 87      attached HDMI, LVDS or DisplayPort encoder chip.
 88
 89  ports:
 90    $ref: /schemas/graph.yaml#/properties/ports
 91
 92    properties:
 93      port@0:
 94        $ref: /schemas/graph.yaml#/properties/port
 95        description: DPI input port
 96
 97      port@1:
 98        $ref: /schemas/graph.yaml#/properties/port
 99        description: DPI output to an HDMI, LVDS or DisplayPort encoder input
100
101    required:
102      - port@0
103      - port@1
104
105  resets:
106    maxItems: 1
107
108  reset-names:
109    items:
110      - const: dpi
111
112required:
113  - compatible
114  - reg
115  - interrupts
116  - clocks
117  - clock-names
118
119oneOf:
120  - required:
121      - port
122  - required:
123      - ports
124
125additionalProperties: false
126
127examples:
128  - |
129    #include <dt-bindings/interrupt-controller/arm-gic.h>
130    #include <dt-bindings/clock/mt8173-clk.h>
131    #include <dt-bindings/power/mt8173-power.h>
132
133    dpi: dpi@1401d000 {
134        compatible = "mediatek,mt8173-dpi";
135        reg = <0x1401d000 0x1000>;
136        interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
137        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
138        clocks = <&mmsys CLK_MM_DPI_PIXEL>,
139             <&mmsys CLK_MM_DPI_ENGINE>,
140             <&apmixedsys CLK_APMIXED_TVDPLL>;
141        clock-names = "pixel", "engine", "pll";
142        pinctrl-names = "default", "sleep";
143        pinctrl-0 = <&dpi_pin_func>;
144        pinctrl-1 = <&dpi_pin_idle>;
145
146        port {
147            dpi0_out: endpoint {
148                remote-endpoint = <&hdmi0_in>;
149            };
150        };
151    };
152
153...