mediatek,dither.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Mediatek display dither processor
  8
  9maintainers:
 10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
 11  - Philipp Zabel <p.zabel@pengutronix.de>
 12
 13description: |
 14  Mediatek display dither processor, namely DITHER, works by approximating
 15  unavailable colors with available colors and by mixing and matching available
 16  colors to mimic unavailable ones.
 17  DITHER device node must be siblings to the central MMSYS_CONFIG node.
 18  For a description of the MMSYS_CONFIG binding, see
 19  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
 20  for details.
 21
 22properties:
 23  compatible:
 24    oneOf:
 25      - enum:
 26          - mediatek,mt8183-disp-dither
 27      - items:
 28          - enum:
 29              - mediatek,mt8186-disp-dither
 30              - mediatek,mt8188-disp-dither
 31              - mediatek,mt8192-disp-dither
 32              - mediatek,mt8195-disp-dither
 33              - mediatek,mt8365-disp-dither
 34          - const: mediatek,mt8183-disp-dither
 35
 36  reg:
 37    maxItems: 1
 38
 39  interrupts:
 40    maxItems: 1
 41
 42  power-domains:
 43    description: A phandle and PM domain specifier as defined by bindings of
 44      the power controller specified by phandle. See
 45      Documentation/devicetree/bindings/power/power-domain.yaml for details.
 46
 47  clocks:
 48    items:
 49      - description: DITHER Clock
 50
 51  mediatek,gce-client-reg:
 52    description: The register of client driver can be configured by gce with
 53      4 arguments defined in this property, such as phandle of gce, subsys id,
 54      register offset and size. Each GCE subsys id is mapping to a client
 55      defined in the header include/dt-bindings/gce/<chip>-gce.h.
 56    $ref: /schemas/types.yaml#/definitions/phandle-array
 57    maxItems: 1
 58
 59  ports:
 60    $ref: /schemas/graph.yaml#/properties/ports
 61    description:
 62      Input and output ports can have multiple endpoints, each of those
 63      connects to either the primary, secondary, etc, display pipeline.
 64
 65    properties:
 66      port@0:
 67        $ref: /schemas/graph.yaml#/properties/port
 68        description: DITHER input, usually from a POSTMASK or GAMMA block.
 69
 70      port@1:
 71        $ref: /schemas/graph.yaml#/properties/port
 72        description:
 73          DITHER output to the input of the next desired component in the
 74          display pipeline, for example one of the available DSC compressors,
 75          DP_INTF, DSI, LVDS or others.
 76
 77    required:
 78      - port@0
 79      - port@1
 80
 81required:
 82  - compatible
 83  - reg
 84  - interrupts
 85  - power-domains
 86  - clocks
 87
 88additionalProperties: false
 89
 90examples:
 91  - |
 92    #include <dt-bindings/interrupt-controller/arm-gic.h>
 93    #include <dt-bindings/clock/mt8183-clk.h>
 94    #include <dt-bindings/power/mt8183-power.h>
 95    #include <dt-bindings/gce/mt8183-gce.h>
 96
 97    soc {
 98        #address-cells = <2>;
 99        #size-cells = <2>;
100
101        dither0: dither@14012000 {
102            compatible = "mediatek,mt8183-disp-dither";
103            reg = <0 0x14012000 0 0x1000>;
104            interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
105            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
106            clocks = <&mmsys CLK_MM_DISP_DITHER0>;
107            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
108        };
109    };