mediatek,ccorr.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Mediatek display color correction
  8
  9maintainers:
 10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
 11  - Philipp Zabel <p.zabel@pengutronix.de>
 12
 13description: |
 14  Mediatek display color correction, namely CCORR, reproduces correct color
 15  on panels with different color gamut.
 16  CCORR device node must be siblings to the central MMSYS_CONFIG node.
 17  For a description of the MMSYS_CONFIG binding, see
 18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
 19  for details.
 20
 21properties:
 22  compatible:
 23    oneOf:
 24      - enum:
 25          - mediatek,mt8183-disp-ccorr
 26          - mediatek,mt8192-disp-ccorr
 27      - items:
 28          - const: mediatek,mt8365-disp-ccorr
 29          - const: mediatek,mt8183-disp-ccorr
 30      - items:
 31          - enum:
 32              - mediatek,mt8186-disp-ccorr
 33              - mediatek,mt8188-disp-ccorr
 34              - mediatek,mt8195-disp-ccorr
 35          - const: mediatek,mt8192-disp-ccorr
 36
 37  reg:
 38    maxItems: 1
 39
 40  interrupts:
 41    maxItems: 1
 42
 43  power-domains:
 44    description: A phandle and PM domain specifier as defined by bindings of
 45      the power controller specified by phandle. See
 46      Documentation/devicetree/bindings/power/power-domain.yaml for details.
 47
 48  clocks:
 49    items:
 50      - description: CCORR Clock
 51
 52  mediatek,gce-client-reg:
 53    description: The register of client driver can be configured by gce with
 54      4 arguments defined in this property, such as phandle of gce, subsys id,
 55      register offset and size. Each GCE subsys id is mapping to a client
 56      defined in the header include/dt-bindings/gce/<chip>-gce.h.
 57    $ref: /schemas/types.yaml#/definitions/phandle-array
 58    maxItems: 1
 59
 60  ports:
 61    $ref: /schemas/graph.yaml#/properties/ports
 62    description:
 63      Input and output ports can have multiple endpoints, each of those
 64      connects to either the primary, secondary, etc, display pipeline.
 65
 66    properties:
 67      port@0:
 68        $ref: /schemas/graph.yaml#/properties/port
 69        description: CCORR input port
 70
 71      port@1:
 72        $ref: /schemas/graph.yaml#/properties/port
 73        description:
 74          CCORR output to the input of the next desired component in the
 75          display pipeline, usually only one of the available AAL blocks.
 76
 77    required:
 78      - port@0
 79      - port@1
 80
 81required:
 82  - compatible
 83  - reg
 84  - interrupts
 85  - power-domains
 86  - clocks
 87
 88additionalProperties: false
 89
 90examples:
 91  - |
 92    #include <dt-bindings/interrupt-controller/arm-gic.h>
 93    #include <dt-bindings/clock/mt8183-clk.h>
 94    #include <dt-bindings/power/mt8183-power.h>
 95    #include <dt-bindings/gce/mt8183-gce.h>
 96
 97    soc {
 98        #address-cells = <2>;
 99        #size-cells = <2>;
100
101        ccorr0: ccorr@1400f000 {
102            compatible = "mediatek,mt8183-disp-ccorr";
103            reg = <0 0x1400f000 0 0x1000>;
104            interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
105            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
106            clocks = <&mmsys CLK_MM_DISP_CCORR0>;
107            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
108        };
109    };