fsl,imx8qxp-dc-display-engine.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-display-engine.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale i.MX8qxp Display Controller Display Engine
  8
  9description:
 10  All Processing Units that operate in a display clock domain. Pixel pipeline
 11  is driven by a video timing and cannot be stalled. Implements all display
 12  specific processing.
 13
 14maintainers:
 15  - Liu Ying <victor.liu@nxp.com>
 16
 17properties:
 18  compatible:
 19    const: fsl,imx8qxp-dc-display-engine
 20
 21  reg:
 22    maxItems: 2
 23
 24  reg-names:
 25    items:
 26      - const: top
 27      - const: cfg
 28
 29  resets:
 30    maxItems: 1
 31
 32  interrupts:
 33    maxItems: 3
 34
 35  interrupt-names:
 36    items:
 37      - const: shdload
 38      - const: framecomplete
 39      - const: seqcomplete
 40
 41  power-domains:
 42    maxItems: 1
 43
 44  "#address-cells":
 45    const: 1
 46
 47  "#size-cells":
 48    const: 1
 49
 50  ranges: true
 51
 52patternProperties:
 53  "^dither@[0-9a-f]+$":
 54    type: object
 55    additionalProperties: true
 56
 57    properties:
 58      compatible:
 59        const: fsl,imx8qxp-dc-dither
 60
 61  "^framegen@[0-9a-f]+$":
 62    type: object
 63    additionalProperties: true
 64
 65    properties:
 66      compatible:
 67        const: fsl,imx8qxp-dc-framegen
 68
 69  "^gammacor@[0-9a-f]+$":
 70    type: object
 71    additionalProperties: true
 72
 73    properties:
 74      compatible:
 75        const: fsl,imx8qxp-dc-gammacor
 76
 77  "^matrix@[0-9a-f]+$":
 78    type: object
 79    additionalProperties: true
 80
 81    properties:
 82      compatible:
 83        const: fsl,imx8qxp-dc-matrix
 84
 85  "^signature@[0-9a-f]+$":
 86    type: object
 87    additionalProperties: true
 88
 89    properties:
 90      compatible:
 91        const: fsl,imx8qxp-dc-signature
 92
 93  "^tcon@[0-9a-f]+$":
 94    type: object
 95    additionalProperties: true
 96
 97    properties:
 98      compatible:
 99        const: fsl,imx8qxp-dc-tcon
100
101required:
102  - compatible
103  - reg
104  - reg-names
105  - interrupts
106  - interrupt-names
107  - power-domains
108  - "#address-cells"
109  - "#size-cells"
110  - ranges
111
112additionalProperties: false
113
114examples:
115  - |
116    #include <dt-bindings/clock/imx8-lpcg.h>
117    #include <dt-bindings/firmware/imx/rsrc.h>
118
119    display-engine@5618b400 {
120        compatible = "fsl,imx8qxp-dc-display-engine";
121        reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
122        reg-names = "top", "cfg";
123        interrupt-parent = <&dc0_intc>;
124        interrupts = <15>, <16>, <17>;
125        interrupt-names = "shdload", "framecomplete", "seqcomplete";
126        power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
127        #address-cells = <1>;
128        #size-cells = <1>;
129        ranges;
130
131        framegen@5618b800 {
132            compatible = "fsl,imx8qxp-dc-framegen";
133            reg = <0x5618b800 0x98>;
134            clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_0>;
135            interrupt-parent = <&dc0_intc>;
136            interrupts = <18>, <19>, <20>, <21>, <41>, <42>, <43>, <44>;
137            interrupt-names = "int0", "int1", "int2", "int3",
138                              "primsync_on", "primsync_off",
139                              "secsync_on", "secsync_off";
140        };
141
142        tcon@5618c800 {
143            compatible = "fsl,imx8qxp-dc-tcon";
144            reg = <0x5618c800 0x588>;
145
146            port {
147                dc0_disp0_dc0_pixel_combiner_ch0: endpoint {
148                    remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_disp0>;
149                };
150            };
151        };
152    };