thine,thc63lvd1024.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/bridge/thine,thc63lvd1024.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Thine Electronics THC63LVD1024 LVDS Decoder
  8
  9maintainers:
 10  - Jacopo Mondi <jacopo+renesas@jmondi.org>
 11  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
 12
 13description: |
 14  The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS
 15  streams to parallel data outputs. The chip supports single/dual input/output
 16  modes, handling up to two LVDS input streams and up to two digital CMOS/TTL
 17  outputs.
 18
 19  Single or dual operation mode, output data mapping and DDR output modes are
 20  configured through input signals and the chip does not expose any control
 21  bus.
 22
 23properties:
 24  compatible:
 25    const: thine,thc63lvd1024
 26
 27  ports:
 28    $ref: /schemas/graph.yaml#/properties/ports
 29    description: |
 30      The device can operate in single or dual input and output modes.
 31
 32      When operating in single input mode, all pixels are received on port@0,
 33      and port@1 shall not contain any endpoint. In dual input mode,
 34      even-numbered pixels are received on port@0 and odd-numbered pixels on
 35      port@1, and both port@0 and port@1 shall contain endpoints.
 36
 37      When operating in single output mode all pixels are output from the first
 38      CMOS/TTL port and port@3 shall not contain any endpoint. In dual output
 39      mode pixels are output from both CMOS/TTL ports and both port@2 and
 40      port@3 shall contain endpoints.
 41
 42    properties:
 43      port@0:
 44        $ref: /schemas/graph.yaml#/properties/port
 45        description: First LVDS input port
 46
 47      port@1:
 48        $ref: /schemas/graph.yaml#/properties/port
 49        description: Second LVDS input port
 50
 51      port@2:
 52        $ref: /schemas/graph.yaml#/properties/port
 53        description: First digital CMOS/TTL parallel output
 54
 55      port@3:
 56        $ref: /schemas/graph.yaml#/properties/port
 57        description: Second digital CMOS/TTL parallel output
 58
 59    required:
 60      - port@0
 61      - port@2
 62
 63  oe-gpios:
 64    maxItems: 1
 65    description: Output enable GPIO signal, pin name "OE", active high.
 66
 67  powerdown-gpios:
 68    maxItems: 1
 69    description: Power down GPIO signal, pin name "/PDWN", active low.
 70
 71  vcc-supply:
 72    description:
 73      Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and
 74      digital circuitry.
 75
 76required:
 77  - compatible
 78  - ports
 79  - vcc-supply
 80
 81additionalProperties: false
 82
 83examples:
 84  - |
 85    #include <dt-bindings/gpio/gpio.h>
 86
 87    lvds-decoder {
 88        compatible = "thine,thc63lvd1024";
 89
 90        vcc-supply = <&reg_lvds_vcc>;
 91        powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 92
 93        ports {
 94            #address-cells = <1>;
 95            #size-cells = <0>;
 96
 97            port@0 {
 98                reg = <0>;
 99
100                lvds_dec_in_0: endpoint {
101                    remote-endpoint = <&lvds_out>;
102                };
103            };
104
105            port@2 {
106                reg = <2>;
107
108                lvds_dec_out_2: endpoint {
109                    remote-endpoint = <&adv7511_in>;
110                };
111            };
112        };
113    };
114
115...