sil,sii8620.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/bridge/sil,sii8620.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Silicon Image SiI8620 HDMI/MHL bridge
  8
  9maintainers:
 10  - Krzysztof Kozlowski <krzk@kernel.org>
 11
 12properties:
 13  compatible:
 14    const: sil,sii8620
 15
 16  reg:
 17    maxItems: 1
 18
 19  clocks:
 20    maxItems: 1
 21
 22  clock-names:
 23    items:
 24      - const: xtal
 25
 26  cvcc10-supply:
 27    description: Digital Core Supply Voltage (1.0V)
 28
 29  interrupts:
 30    maxItems: 1
 31
 32  iovcc18-supply:
 33    description: I/O Supply Voltage (1.8V)
 34
 35  reset-gpios:
 36    maxItems: 1
 37
 38  ports:
 39    $ref: /schemas/graph.yaml#/properties/ports
 40    unevaluatedProperties: false
 41
 42    properties:
 43      port@0:
 44        $ref: /schemas/graph.yaml#/properties/port
 45        description:
 46          Video port for HDMI (encoder) input
 47
 48      port@1:
 49        $ref: /schemas/graph.yaml#/properties/port
 50        description:
 51          MHL to connector port
 52
 53    required:
 54      - port@0
 55      - port@1
 56
 57required:
 58  - compatible
 59  - reg
 60  - clocks
 61  - cvcc10-supply
 62  - interrupts
 63  - iovcc18-supply
 64  - reset-gpios
 65  - ports
 66
 67additionalProperties: false
 68
 69examples:
 70  - |
 71    #include <dt-bindings/gpio/gpio.h>
 72    #include <dt-bindings/interrupt-controller/irq.h>
 73
 74    i2c {
 75        #address-cells = <1>;
 76        #size-cells = <0>;
 77
 78        bridge@39 {
 79            reg = <0x39>;
 80            compatible = "sil,sii8620";
 81            cvcc10-supply = <&ldo36_reg>;
 82            iovcc18-supply = <&ldo34_reg>;
 83            interrupt-parent = <&gpf0>;
 84            interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 85            reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
 86            clocks = <&pmu_system_controller 0>;
 87            clock-names = "xtal";
 88
 89            ports {
 90                #address-cells = <1>;
 91                #size-cells = <0>;
 92
 93                port@0 {
 94                    reg = <0>;
 95                    mhl_to_hdmi: endpoint {
 96                        remote-endpoint = <&hdmi_to_mhl>;
 97                    };
 98                };
 99
100                port@1 {
101                    reg = <1>;
102                    mhl_to_musb_con: endpoint {
103                        remote-endpoint = <&musb_con_to_mhl>;
104                    };
105                };
106            };
107        };
108    };