nwl-dsi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Northwest Logic MIPI-DSI controller on i.MX SoCs
  8
  9maintainers:
 10  - Guido Gúnther <agx@sigxcpu.org>
 11  - Robert Chiras <robert.chiras@nxp.com>
 12
 13description: |
 14  NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
 15  the SOCs NWL MIPI-DSI host controller.
 16
 17allOf:
 18  - $ref: ../dsi-controller.yaml#
 19
 20properties:
 21  compatible:
 22    const: fsl,imx8mq-nwl-dsi
 23
 24  reg:
 25    maxItems: 1
 26
 27  interrupts:
 28    maxItems: 1
 29
 30  '#address-cells':
 31    const: 1
 32
 33  '#size-cells':
 34    const: 0
 35
 36  assigned-clock-parents: true
 37  assigned-clock-rates: true
 38  assigned-clocks: true
 39
 40  clocks:
 41    items:
 42      - description: DSI core clock
 43      - description: RX_ESC clock (used in escape mode)
 44      - description: TX_ESC clock (used in escape mode)
 45      - description: PHY_REF clock
 46      - description: LCDIF clock
 47
 48  clock-names:
 49    items:
 50      - const: core
 51      - const: rx_esc
 52      - const: tx_esc
 53      - const: phy_ref
 54      - const: lcdif
 55
 56  mux-controls:
 57    description:
 58      mux controller node to use for operating the input mux
 59
 60  phys:
 61    maxItems: 1
 62    description:
 63      A phandle to the phy module representing the DPHY
 64
 65  phy-names:
 66    items:
 67      - const: dphy
 68
 69  power-domains:
 70    maxItems: 1
 71
 72  resets:
 73    items:
 74      - description: dsi byte reset line
 75      - description: dsi dpi reset line
 76      - description: dsi esc reset line
 77      - description: dsi pclk reset line
 78
 79  reset-names:
 80    items:
 81      - const: byte
 82      - const: dpi
 83      - const: esc
 84      - const: pclk
 85
 86  ports:
 87    $ref: /schemas/graph.yaml#/properties/ports
 88
 89    properties:
 90      port@0:
 91        $ref: /schemas/graph.yaml#/$defs/port-base
 92        description:
 93          Input port node to receive pixel data from the
 94          display controller. Exactly one endpoint must be
 95          specified.
 96        properties:
 97          endpoint@0:
 98            $ref: /schemas/graph.yaml#/properties/endpoint
 99            description: sub-node describing the input from LCDIF
100
101          endpoint@1:
102            $ref: /schemas/graph.yaml#/properties/endpoint
103            description: sub-node describing the input from DCSS
104
105        oneOf:
106          - required:
107              - endpoint@0
108          - required:
109              - endpoint@1
110
111        unevaluatedProperties: false
112
113      port@1:
114        $ref: /schemas/graph.yaml#/$defs/port-base
115        unevaluatedProperties: false
116        description:
117          DSI output port node to the panel or the next bridge
118          in the chain
119
120        properties:
121          endpoint:
122            $ref: /schemas/media/video-interfaces.yaml#
123            unevaluatedProperties: false
124
125            properties:
126              data-lanes:
127                description: array of physical DSI data lane indexes.
128                minItems: 1
129                items:
130                  - const: 1
131                  - const: 2
132                  - const: 3
133                  - const: 4
134
135    required:
136      - port@0
137      - port@1
138
139required:
140  - '#address-cells'
141  - '#size-cells'
142  - clock-names
143  - clocks
144  - compatible
145  - interrupts
146  - mux-controls
147  - phy-names
148  - phys
149  - ports
150  - reg
151  - reset-names
152  - resets
153
154unevaluatedProperties: false
155
156examples:
157  - |
158    #include <dt-bindings/clock/imx8mq-clock.h>
159    #include <dt-bindings/gpio/gpio.h>
160    #include <dt-bindings/interrupt-controller/arm-gic.h>
161    #include <dt-bindings/reset/imx8mq-reset.h>
162
163    dsi@30a00000 {
164              #address-cells = <1>;
165              #size-cells = <0>;
166              compatible = "fsl,imx8mq-nwl-dsi";
167              reg = <0x30A00000 0x300>;
168              clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
169                       <&clk IMX8MQ_CLK_DSI_AHB>,
170                       <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
171                       <&clk IMX8MQ_CLK_DSI_PHY_REF>,
172                       <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
173              clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
174              interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
175              mux-controls = <&mux 0>;
176              power-domains = <&pgc_mipi>;
177              resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
178                       <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
179                       <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
180                       <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
181              reset-names = "byte", "dpi", "esc", "pclk";
182              phys = <&dphy>;
183              phy-names = "dphy";
184
185              panel@0 {
186                      compatible = "rocktech,jh057n00900";
187                      reg = <0>;
188                      vcc-supply = <&reg_2v8_p>;
189                      iovcc-supply = <&reg_1v8_p>;
190                      reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
191                      port {
192                           panel_in: endpoint {
193                                     remote-endpoint = <&mipi_dsi_out>;
194                           };
195                      };
196              };
197
198              ports {
199                    #address-cells = <1>;
200                    #size-cells = <0>;
201
202                    port@0 {
203                           #size-cells = <0>;
204                           #address-cells = <1>;
205                           reg = <0>;
206                           mipi_dsi_in: endpoint@0 {
207                                        reg = <0>;
208                                        remote-endpoint = <&lcdif_mipi_dsi>;
209                           };
210                    };
211                    port@1 {
212                           reg = <1>;
213                           mipi_dsi_out: endpoint {
214                                         remote-endpoint = <&panel_in>;
215                           };
216                    };
217              };
218    };