fsl,ldb.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/bridge/fsl,ldb.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale i.MX8MP DPI to LVDS bridge chip
  8
  9maintainers:
 10  - Marek Vasut <marex@denx.de>
 11
 12description: |
 13  The i.MX8MP mediamix contains two registers which are responsible
 14  for configuring the on-SoC DPI-to-LVDS serializer. This describes
 15  those registers as bridge within the DT.
 16
 17properties:
 18  compatible:
 19    enum:
 20      - fsl,imx6sx-ldb
 21      - fsl,imx8mp-ldb
 22      - fsl,imx93-ldb
 23
 24  clocks:
 25    maxItems: 1
 26
 27  clock-names:
 28    const: ldb
 29
 30  reg:
 31    maxItems: 2
 32
 33  reg-names:
 34    items:
 35      - const: ldb
 36      - const: lvds
 37
 38  ports:
 39    $ref: /schemas/graph.yaml#/properties/ports
 40
 41    properties:
 42      port@0:
 43        $ref: /schemas/graph.yaml#/properties/port
 44        description: Video port for DPI input.
 45
 46      port@1:
 47        $ref: /schemas/graph.yaml#/properties/port
 48        description: Video port for LVDS Channel-A output (panel or bridge).
 49
 50      port@2:
 51        $ref: /schemas/graph.yaml#/properties/port
 52        description: Video port for LVDS Channel-B output (panel or bridge).
 53
 54    required:
 55      - port@0
 56      - port@1
 57
 58required:
 59  - compatible
 60  - clocks
 61  - ports
 62
 63allOf:
 64  - if:
 65      properties:
 66        compatible:
 67          contains:
 68            enum:
 69              - fsl,imx6sx-ldb
 70              - fsl,imx93-ldb
 71    then:
 72      properties:
 73        ports:
 74          properties:
 75            port@2: false
 76
 77additionalProperties: false
 78
 79examples:
 80  - |
 81    #include <dt-bindings/clock/imx8mp-clock.h>
 82
 83    blk-ctrl {
 84        #address-cells = <1>;
 85        #size-cells = <1>;
 86
 87        bridge@5c {
 88            compatible = "fsl,imx8mp-ldb";
 89            clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
 90            clock-names = "ldb";
 91            reg = <0x5c 0x4>, <0x128 0x4>;
 92            reg-names = "ldb", "lvds";
 93
 94            ports {
 95                #address-cells = <1>;
 96                #size-cells = <0>;
 97
 98                port@0 {
 99                    reg = <0>;
100
101                    ldb_from_lcdif2: endpoint {
102                        remote-endpoint = <&lcdif2_to_ldb>;
103                    };
104                };
105
106                port@1 {
107                    reg = <1>;
108
109                    ldb_lvds_ch0: endpoint {
110                        remote-endpoint = <&ldb_to_lvdsx4panel>;
111                    };
112                };
113
114                port@2 {
115                    reg = <2>;
116
117                    ldb_lvds_ch1: endpoint {
118                    };
119                };
120            };
121        };
122    };