fsl,imx93-mipi-dsi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale i.MX93 specific extensions to Synopsys Designware MIPI DSI
  8
  9maintainers:
 10  - Liu Ying <victor.liu@nxp.com>
 11
 12description: |
 13  There is a Synopsys Designware MIPI DSI Host Controller and a Synopsys
 14  Designware MIPI DPHY embedded in Freescale i.MX93 SoC.  Some configurations
 15  and extensions to them are controlled by i.MX93 media blk-ctrl.
 16
 17allOf:
 18  - $ref: snps,dw-mipi-dsi.yaml#
 19
 20properties:
 21  compatible:
 22    const: fsl,imx93-mipi-dsi
 23
 24  clocks:
 25    items:
 26      - description: apb clock
 27      - description: pixel clock
 28      - description: PHY configuration clock
 29      - description: PHY reference clock
 30
 31  clock-names:
 32    items:
 33      - const: pclk
 34      - const: pix
 35      - const: phy_cfg
 36      - const: phy_ref
 37
 38  interrupts:
 39    maxItems: 1
 40
 41  fsl,media-blk-ctrl:
 42    $ref: /schemas/types.yaml#/definitions/phandle
 43    description:
 44      i.MX93 media blk-ctrl, as a syscon, controls pixel component bit map
 45      configurations from LCDIF display controller to the MIPI DSI host
 46      controller and MIPI DPHY PLL related configurations through PLL SoC
 47      interface.
 48
 49  power-domains:
 50    maxItems: 1
 51
 52required:
 53  - compatible
 54  - interrupts
 55  - fsl,media-blk-ctrl
 56  - power-domains
 57
 58unevaluatedProperties: false
 59
 60examples:
 61  - |
 62    #include <dt-bindings/clock/imx93-clock.h>
 63    #include <dt-bindings/gpio/gpio.h>
 64    #include <dt-bindings/interrupt-controller/arm-gic.h>
 65    #include <dt-bindings/power/fsl,imx93-power.h>
 66
 67    dsi@4ae10000 {
 68        compatible = "fsl,imx93-mipi-dsi";
 69        reg = <0x4ae10000 0x10000>;
 70        interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 71        clocks = <&clk IMX93_CLK_MIPI_DSI_GATE>,
 72                 <&clk IMX93_CLK_MEDIA_DISP_PIX>,
 73                 <&clk IMX93_CLK_MIPI_PHY_CFG>,
 74                 <&clk IMX93_CLK_24M>;
 75        clock-names = "pclk", "pix", "phy_cfg", "phy_ref";
 76        fsl,media-blk-ctrl = <&media_blk_ctrl>;
 77        power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>;
 78        #address-cells = <1>;
 79        #size-cells = <0>;
 80
 81        panel@0 {
 82            compatible = "raydium,rm67191";
 83            reg = <0>;
 84            reset-gpios = <&adp5585gpio 6 GPIO_ACTIVE_LOW>;
 85            dsi-lanes = <4>;
 86            video-mode = <2>;
 87
 88            port {
 89                panel_in: endpoint {
 90                    remote-endpoint = <&dsi_out>;
 91                };
 92            };
 93        };
 94
 95        ports {
 96            #address-cells = <1>;
 97            #size-cells = <0>;
 98
 99            port@0 {
100                reg = <0>;
101
102                dsi_to_lcdif: endpoint {
103                    remote-endpoint = <&lcdif_to_dsi>;
104                };
105            };
106
107            port@1 {
108                reg = <1>;
109
110                dsi_out: endpoint {
111                    remote-endpoint = <&panel_in>;
112                };
113            };
114        };
115    };