fsl,imx8mp-hdmi-tx.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale i.MX8MP DWC HDMI TX Encoder
  8
  9maintainers:
 10  - Lucas Stach <l.stach@pengutronix.de>
 11
 12description:
 13  The i.MX8MP HDMI transmitter is a Synopsys DesignWare
 14  HDMI 2.0a TX controller IP.
 15
 16allOf:
 17  - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml#
 18
 19properties:
 20  compatible:
 21    enum:
 22      - fsl,imx8mp-hdmi-tx
 23
 24  reg-io-width:
 25    const: 1
 26
 27  clocks:
 28    maxItems: 4
 29
 30  clock-names:
 31    items:
 32      - const: iahb
 33      - const: isfr
 34      - const: cec
 35      - const: pix
 36
 37  power-domains:
 38    maxItems: 1
 39
 40  ports:
 41    $ref: /schemas/graph.yaml#/properties/ports
 42
 43    properties:
 44      port@0:
 45        $ref: /schemas/graph.yaml#/properties/port
 46        description: Parallel RGB input port
 47
 48      port@1:
 49        $ref: /schemas/graph.yaml#/properties/port
 50        description: HDMI output port
 51
 52      port@2:
 53        $ref: /schemas/graph.yaml#/properties/port
 54        description: Parallel audio input port
 55
 56    required:
 57      - port@0
 58      - port@1
 59
 60required:
 61  - compatible
 62  - reg
 63  - clocks
 64  - clock-names
 65  - interrupts
 66  - power-domains
 67  - ports
 68
 69unevaluatedProperties: false
 70
 71examples:
 72  - |
 73    #include <dt-bindings/clock/imx8mp-clock.h>
 74    #include <dt-bindings/interrupt-controller/irq.h>
 75    #include <dt-bindings/power/imx8mp-power.h>
 76
 77    hdmi@32fd8000 {
 78        compatible = "fsl,imx8mp-hdmi-tx";
 79        reg = <0x32fd8000 0x7eff>;
 80        interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 81        clocks = <&clk IMX8MP_CLK_HDMI_APB>,
 82                 <&clk IMX8MP_CLK_HDMI_REF_266M>,
 83                 <&clk IMX8MP_CLK_32K>,
 84                 <&hdmi_tx_phy>;
 85        clock-names = "iahb", "isfr", "cec", "pix";
 86        power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
 87        reg-io-width = <1>;
 88        ports {
 89            #address-cells = <1>;
 90            #size-cells = <0>;
 91            port@0 {
 92                reg = <0>;
 93
 94                endpoint {
 95                    remote-endpoint = <&pvi_to_hdmi_tx>;
 96                };
 97            };
 98
 99            port@1 {
100                reg = <1>;
101                endpoint {
102                    remote-endpoint = <&hdmi0_con>;
103                };
104            };
105
106            port@2 {
107                reg = <2>;
108
109                endpoint {
110                    remote-endpoint = <&pai_to_hdmi_tx>;
111                };
112            };
113        };
114    };