nvidia,tegra30-actmon.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NVIDIA Tegra30 Activity Monitor
  8
  9maintainers:
 10  - Dmitry Osipenko <digetx@gmail.com>
 11  - Jon Hunter <jonathanh@nvidia.com>
 12  - Thierry Reding <thierry.reding@gmail.com>
 13
 14description: |
 15  The activity monitor block collects statistics about the behaviour of other
 16  components in the system. This information can be used to derive the rate at
 17  which the external memory needs to be clocked in order to serve all requests
 18  from the monitored clients.
 19
 20properties:
 21  compatible:
 22    oneOf:
 23      - enum:
 24          - nvidia,tegra30-actmon
 25          - nvidia,tegra114-actmon
 26          - nvidia,tegra124-actmon
 27      - items:
 28          - const: nvidia,tegra210-actmon
 29          - const: nvidia,tegra124-actmon
 30
 31  reg:
 32    maxItems: 1
 33
 34  clocks:
 35    maxItems: 2
 36
 37  clock-names:
 38    items:
 39      - const: actmon
 40      - const: emc
 41
 42  resets:
 43    maxItems: 1
 44
 45  reset-names:
 46    items:
 47      - const: actmon
 48
 49  interrupts:
 50    maxItems: 1
 51
 52  interconnects:
 53    minItems: 1
 54    maxItems: 12
 55
 56  interconnect-names:
 57    minItems: 1
 58    maxItems: 12
 59    description:
 60      Should include name of the interconnect path for each interconnect
 61      entry. Consult TRM documentation for information about available
 62      memory clients, see MEMORY CONTROLLER and ACTIVITY MONITOR sections.
 63
 64  operating-points-v2:
 65    description:
 66      Should contain freqs and voltages and opp-supported-hw property, which
 67      is a bitfield indicating SoC speedo ID mask.
 68
 69  "#cooling-cells":
 70    const: 2
 71
 72required:
 73  - compatible
 74  - reg
 75  - clocks
 76  - clock-names
 77  - resets
 78  - reset-names
 79  - interrupts
 80  - interconnects
 81  - interconnect-names
 82  - operating-points-v2
 83  - "#cooling-cells"
 84
 85additionalProperties: false
 86
 87examples:
 88  - |
 89    #include <dt-bindings/memory/tegra30-mc.h>
 90
 91    mc: memory-controller@7000f000 {
 92        compatible = "nvidia,tegra30-mc";
 93        reg = <0x7000f000 0x400>;
 94        clocks = <&clk 32>;
 95        clock-names = "mc";
 96
 97        interrupts = <0 77 4>;
 98
 99        #iommu-cells = <1>;
100        #reset-cells = <1>;
101        #interconnect-cells = <1>;
102    };
103
104    emc: external-memory-controller@7000f400 {
105        compatible = "nvidia,tegra30-emc";
106        reg = <0x7000f400 0x400>;
107        interrupts = <0 78 4>;
108        clocks = <&clk 57>;
109
110        nvidia,memory-controller = <&mc>;
111        operating-points-v2 = <&dvfs_opp_table>;
112        power-domains = <&domain>;
113
114        #interconnect-cells = <0>;
115    };
116
117    actmon@6000c800 {
118        compatible = "nvidia,tegra30-actmon";
119        reg = <0x6000c800 0x400>;
120        interrupts = <0 45 4>;
121        clocks = <&clk 119>, <&clk 57>;
122        clock-names = "actmon", "emc";
123        resets = <&rst 119>;
124        reset-names = "actmon";
125        operating-points-v2 = <&dvfs_opp_table>;
126        interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
127        interconnect-names = "cpu-read";
128        #cooling-cells = <2>;
129    };