qcom-qce.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm crypto engine driver
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Konrad Dybcio <konradybcio@kernel.org>
 12
 13description:
 14  This document defines the binding for the QCE crypto
 15  controller found on Qualcomm parts.
 16
 17properties:
 18  compatible:
 19    oneOf:
 20      - const: qcom,crypto-v5.1
 21        deprecated: true
 22        description: Kept only for ABI backward compatibility
 23
 24      - const: qcom,crypto-v5.4
 25        deprecated: true
 26        description: Kept only for ABI backward compatibility
 27
 28      - items:
 29          - enum:
 30              - qcom,ipq4019-qce
 31              - qcom,sm8150-qce
 32          - const: qcom,qce
 33
 34      - items:
 35          - enum:
 36              - qcom,ipq6018-qce
 37              - qcom,ipq8074-qce
 38              - qcom,ipq9574-qce
 39              - qcom,msm8996-qce
 40              - qcom,qcm2290-qce
 41              - qcom,sdm845-qce
 42              - qcom,sm6115-qce
 43          - const: qcom,ipq4019-qce
 44          - const: qcom,qce
 45
 46      - items:
 47          - enum:
 48              - qcom,kaanapali-qce
 49              - qcom,qcs615-qce
 50              - qcom,qcs8300-qce
 51              - qcom,sa8775p-qce
 52              - qcom,sc7280-qce
 53              - qcom,sm6350-qce
 54              - qcom,sm8250-qce
 55              - qcom,sm8350-qce
 56              - qcom,sm8450-qce
 57              - qcom,sm8550-qce
 58              - qcom,sm8650-qce
 59              - qcom,sm8750-qce
 60              - qcom,x1e80100-qce
 61          - const: qcom,sm8150-qce
 62          - const: qcom,qce
 63
 64  reg:
 65    maxItems: 1
 66
 67  clocks:
 68    minItems: 1
 69    maxItems: 3
 70
 71  clock-names:
 72    minItems: 1
 73    maxItems: 3
 74
 75  iommus:
 76    minItems: 1
 77    maxItems: 8
 78    description:
 79      phandle to apps_smmu node with sid mask.
 80
 81  interconnects:
 82    maxItems: 1
 83    description:
 84      Interconnect path between qce crypto and main memory.
 85
 86  interconnect-names:
 87    const: memory
 88
 89  dmas:
 90    items:
 91      - description: DMA specifiers for rx dma channel.
 92      - description: DMA specifiers for tx dma channel.
 93
 94  dma-names:
 95    items:
 96      - const: rx
 97      - const: tx
 98
 99allOf:
100  - if:
101      properties:
102        compatible:
103          contains:
104            enum:
105              - qcom,crypto-v5.1
106              - qcom,crypto-v5.4
107              - qcom,ipq6018-qce
108              - qcom,ipq8074-qce
109              - qcom,ipq9574-qce
110              - qcom,msm8996-qce
111              - qcom,sdm845-qce
112    then:
113      properties:
114        clocks:
115          maxItems: 3
116        clock-names:
117          items:
118            - const: iface
119            - const: bus
120            - const: core
121      required:
122        - clocks
123        - clock-names
124
125  - if:
126      properties:
127        compatible:
128          contains:
129            enum:
130              - qcom,qcm2290-qce
131              - qcom,sm6115-qce
132    then:
133      properties:
134        clocks:
135          maxItems: 1
136        clock-names:
137          items:
138            - const: core
139      required:
140        - clocks
141        - clock-names
142
143  - if:
144      properties:
145        compatible:
146          contains:
147            enum:
148              - qcom,sm8150-qce
149    then:
150      properties:
151        clocks: false
152        clock-names: false
153
154required:
155  - compatible
156  - reg
157  - dmas
158  - dma-names
159
160additionalProperties: false
161
162examples:
163  - |
164    #include <dt-bindings/clock/qcom,gcc-apq8084.h>
165    crypto-engine@fd45a000 {
166        compatible = "qcom,ipq6018-qce", "qcom,ipq4019-qce", "qcom,qce";
167        reg = <0xfd45a000 0x6000>;
168        clocks = <&gcc GCC_CE2_AHB_CLK>,
169                 <&gcc GCC_CE2_AXI_CLK>,
170                 <&gcc GCC_CE2_CLK>;
171        clock-names = "iface", "bus", "core";
172        dmas = <&cryptobam 2>, <&cryptobam 3>;
173        dma-names = "rx", "tx";
174        iommus = <&apps_smmu 0x584 0x0011>,
175                 <&apps_smmu 0x586 0x0011>,
176                 <&apps_smmu 0x594 0x0011>,
177                 <&apps_smmu 0x596 0x0011>;
178    };