hisilicon,hip06-sec.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/crypto/hisilicon,hip06-sec.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Hisilicon hip06/hip07 Security Accelerator
  8
  9maintainers:
 10  - Jonathan Cameron <Jonathan.Cameron@huawei.com>
 11
 12properties:
 13  compatible:
 14    enum:
 15      - hisilicon,hip06-sec
 16      - hisilicon,hip07-sec
 17
 18  reg:
 19    items:
 20      - description: Registers for backend processing engines
 21      - description: Registers for common functionality
 22      - description: Registers for queue 0
 23      - description: Registers for queue 1
 24      - description: Registers for queue 2
 25      - description: Registers for queue 3
 26      - description: Registers for queue 4
 27      - description: Registers for queue 5
 28      - description: Registers for queue 6
 29      - description: Registers for queue 7
 30      - description: Registers for queue 8
 31      - description: Registers for queue 9
 32      - description: Registers for queue 10
 33      - description: Registers for queue 11
 34      - description: Registers for queue 12
 35      - description: Registers for queue 13
 36      - description: Registers for queue 14
 37      - description: Registers for queue 15
 38
 39  interrupts:
 40    items:
 41      - description: SEC unit error queue interrupt
 42      - description: Completion interrupt for queue 0
 43      - description: Error interrupt for queue 0
 44      - description: Completion interrupt for queue 1
 45      - description: Error interrupt for queue 1
 46      - description: Completion interrupt for queue 2
 47      - description: Error interrupt for queue 2
 48      - description: Completion interrupt for queue 3
 49      - description: Error interrupt for queue 3
 50      - description: Completion interrupt for queue 4
 51      - description: Error interrupt for queue 4
 52      - description: Completion interrupt for queue 5
 53      - description: Error interrupt for queue 5
 54      - description: Completion interrupt for queue 6
 55      - description: Error interrupt for queue 6
 56      - description: Completion interrupt for queue 7
 57      - description: Error interrupt for queue 7
 58      - description: Completion interrupt for queue 8
 59      - description: Error interrupt for queue 8
 60      - description: Completion interrupt for queue 9
 61      - description: Error interrupt for queue 9
 62      - description: Completion interrupt for queue 10
 63      - description: Error interrupt for queue 10
 64      - description: Completion interrupt for queue 11
 65      - description: Error interrupt for queue 11
 66      - description: Completion interrupt for queue 12
 67      - description: Error interrupt for queue 12
 68      - description: Completion interrupt for queue 13
 69      - description: Error interrupt for queue 13
 70      - description: Completion interrupt for queue 14
 71      - description: Error interrupt for queue 14
 72      - description: Completion interrupt for queue 15
 73      - description: Error interrupt for queue 15
 74
 75  dma-coherent: true
 76
 77  iommus:
 78    maxItems: 1
 79
 80required:
 81  - compatible
 82  - reg
 83  - interrupts
 84  - dma-coherent
 85
 86additionalProperties: false
 87
 88examples:
 89  - |
 90    bus {
 91        #address-cells = <2>;
 92        #size-cells = <2>;
 93
 94        crypto@400d2000000 {
 95            compatible = "hisilicon,hip07-sec";
 96            reg = <0x400 0xd0000000 0x0 0x10000
 97                  0x400 0xd2000000 0x0 0x10000
 98                  0x400 0xd2010000 0x0 0x10000
 99                  0x400 0xd2020000 0x0 0x10000
100                  0x400 0xd2030000 0x0 0x10000
101                  0x400 0xd2040000 0x0 0x10000
102                  0x400 0xd2050000 0x0 0x10000
103                  0x400 0xd2060000 0x0 0x10000
104                  0x400 0xd2070000 0x0 0x10000
105                  0x400 0xd2080000 0x0 0x10000
106                  0x400 0xd2090000 0x0 0x10000
107                  0x400 0xd20a0000 0x0 0x10000
108                  0x400 0xd20b0000 0x0 0x10000
109                  0x400 0xd20c0000 0x0 0x10000
110                  0x400 0xd20d0000 0x0 0x10000
111                  0x400 0xd20e0000 0x0 0x10000
112                  0x400 0xd20f0000 0x0 0x10000
113                  0x400 0xd2100000 0x0 0x10000>;
114            interrupts = <576 4>,
115                        <577 1>, <578 4>,
116                        <579 1>, <580 4>,
117                        <581 1>, <582 4>,
118                        <583 1>, <584 4>,
119                        <585 1>, <586 4>,
120                        <587 1>, <588 4>,
121                        <589 1>, <590 4>,
122                        <591 1>, <592 4>,
123                        <593 1>, <594 4>,
124                        <595 1>, <596 4>,
125                        <597 1>, <598 4>,
126                        <599 1>, <600 4>,
127                        <601 1>, <602 4>,
128                        <603 1>, <604 4>,
129                        <605 1>, <606 4>,
130                        <607 1>, <608 4>;
131            dma-coherent;
132            iommus = <&p1_smmu_alg_a 0x600>;
133        };
134    };