apple,cluster-cpufreq.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Apple SoC cluster cpufreq device
  8
  9maintainers:
 10  - Hector Martin <marcan@marcan.st>
 11
 12description: |
 13  Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
 14  the cluster management register block. This binding uses the standard
 15  operating-points-v2 table to define the CPU performance states, with the
 16  opp-level property specifying the hardware p-state index for that level.
 17
 18properties:
 19  compatible:
 20    oneOf:
 21      - items:
 22          - enum:
 23              - apple,t8103-cluster-cpufreq
 24              - apple,t8112-cluster-cpufreq
 25          - const: apple,cluster-cpufreq
 26      - items:
 27          - enum:
 28              - apple,s8000-cluster-cpufreq
 29              - apple,t8010-cluster-cpufreq
 30              - apple,t8015-cluster-cpufreq
 31              - apple,t6000-cluster-cpufreq
 32          - const: apple,t8103-cluster-cpufreq
 33          - const: apple,cluster-cpufreq
 34      - items:
 35          - const: apple,t7000-cluster-cpufreq
 36          - const: apple,s5l8960x-cluster-cpufreq
 37      - const: apple,s5l8960x-cluster-cpufreq
 38      - items:
 39          - const: apple,t6020-cluster-cpufreq
 40          - const: apple,t8112-cluster-cpufreq
 41
 42  reg:
 43    maxItems: 1
 44
 45  '#performance-domain-cells':
 46    const: 0
 47
 48required:
 49  - compatible
 50  - reg
 51  - '#performance-domain-cells'
 52
 53additionalProperties: false
 54
 55examples:
 56  - |
 57    // This example shows a single CPU per domain and 2 domains,
 58    // with two p-states per domain.
 59    // Shipping hardware has 2-4 CPUs per domain and 2-6 domains.
 60    cpus {
 61      #address-cells = <2>;
 62      #size-cells = <0>;
 63
 64      cpu@0 {
 65        compatible = "apple,icestorm";
 66        device_type = "cpu";
 67        reg = <0x0 0x0>;
 68        operating-points-v2 = <&ecluster_opp>;
 69        performance-domains = <&cpufreq_e>;
 70      };
 71
 72      cpu@10100 {
 73        compatible = "apple,firestorm";
 74        device_type = "cpu";
 75        reg = <0x0 0x10100>;
 76        operating-points-v2 = <&pcluster_opp>;
 77        performance-domains = <&cpufreq_p>;
 78      };
 79    };
 80
 81    ecluster_opp: opp-table-0 {
 82      compatible = "operating-points-v2";
 83      opp-shared;
 84
 85      opp01 {
 86        opp-hz = /bits/ 64 <600000000>;
 87        opp-level = <1>;
 88        clock-latency-ns = <7500>;
 89      };
 90      opp02 {
 91        opp-hz = /bits/ 64 <972000000>;
 92        opp-level = <2>;
 93        clock-latency-ns = <22000>;
 94      };
 95    };
 96
 97    pcluster_opp: opp-table-1 {
 98      compatible = "operating-points-v2";
 99      opp-shared;
100
101      opp01 {
102        opp-hz = /bits/ 64 <600000000>;
103        opp-level = <1>;
104        clock-latency-ns = <8000>;
105      };
106      opp02 {
107        opp-hz = /bits/ 64 <828000000>;
108        opp-level = <2>;
109        clock-latency-ns = <19000>;
110      };
111    };
112
113    soc {
114      #address-cells = <2>;
115      #size-cells = <2>;
116
117      cpufreq_e: performance-controller@210e20000 {
118        compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
119        reg = <0x2 0x10e20000 0 0x1000>;
120        #performance-domain-cells = <0>;
121      };
122
123      cpufreq_p: performance-controller@211e20000 {
124        compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
125        reg = <0x2 0x11e20000 0 0x1000>;
126        #performance-domain-cells = <0>;
127      };
128    };