xlnx,versal-clk.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Xilinx Versal clock controller
  8
  9maintainers:
 10  - Michal Simek <michal.simek@amd.com>
 11
 12description: |
 13  The clock controller is a hardware block of Xilinx versal clock tree. It
 14  reads required input clock frequencies from the devicetree and acts as clock
 15  provider for all clock consumers of PS clocks.
 16
 17properties:
 18  compatible:
 19    oneOf:
 20      - enum:
 21          - xlnx,versal-clk
 22          - xlnx,zynqmp-clk
 23      - items:
 24          - enum:
 25              - xlnx,versal-net-clk
 26          - const: xlnx,versal-clk
 27
 28  "#clock-cells":
 29    const: 1
 30
 31  clocks:
 32    description: List of clock specifiers which are external input
 33      clocks to the given clock controller.
 34    minItems: 2
 35    maxItems: 8
 36
 37  clock-names:
 38    minItems: 2
 39    maxItems: 8
 40
 41required:
 42  - compatible
 43  - "#clock-cells"
 44  - clocks
 45  - clock-names
 46
 47additionalProperties: false
 48
 49allOf:
 50  - if:
 51      properties:
 52        compatible:
 53          contains:
 54            enum:
 55              - xlnx,versal-clk
 56
 57    then:
 58      properties:
 59        clocks:
 60          items:
 61            - description: reference clock
 62            - description: alternate reference clock for programmable logic
 63
 64        clock-names:
 65          items:
 66            - const: ref
 67            - const: pl_alt_ref
 68
 69  - if:
 70      properties:
 71        compatible:
 72          contains:
 73            enum:
 74              - xlnx,versal-net-clk
 75
 76    then:
 77      properties:
 78        clocks:
 79          items:
 80            - description: reference clock
 81            - description: alternate reference clock for programmable logic
 82            - description: alternate reference clock
 83
 84        clock-names:
 85          items:
 86            - const: ref
 87            - const: pl_alt_ref
 88            - const: alt_ref
 89
 90  - if:
 91      properties:
 92        compatible:
 93          contains:
 94            enum:
 95              - xlnx,zynqmp-clk
 96
 97    then:
 98      properties:
 99        clocks:
100          minItems: 5
101          items:
102            - description: PS reference clock
103            - description: reference clock for video system
104            - description: alternative PS reference clock
105            - description: auxiliary reference clock
106            - description: transceiver reference clock
107            - description: (E)MIO clock source  (Optional clock)
108            - description: GEM emio clock  (Optional clock)
109            - description: Watchdog external clock (Optional clock)
110
111        clock-names:
112          minItems: 5
113          items:
114            - const: pss_ref_clk
115            - const: video_clk
116            - const: pss_alt_ref_clk
117            - const: aux_ref_clk
118            - const: gt_crx_ref_clk
119            - pattern: "^mio_clk[00-77]+.*$"
120            - pattern: "gem[0-3]+_emio_clk.*$"
121            - pattern: "swdt[0-1]+_ext_clk.*$"
122
123examples:
124  - |
125    firmware {
126      zynqmp_firmware: zynqmp-firmware {
127        compatible = "xlnx,zynqmp-firmware";
128        method = "smc";
129        versal_clk: clock-controller {
130          #clock-cells = <1>;
131          compatible = "xlnx,versal-clk";
132          clocks = <&ref>,  <&pl_alt_ref>;
133          clock-names = "ref", "pl_alt_ref";
134        };
135      };
136    };
137
138    clock-controller {
139        #clock-cells = <1>;
140        compatible = "xlnx,zynqmp-clk";
141        clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
142                 <&aux_ref_clk>, <&gt_crx_ref_clk>;
143        clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
144                      "aux_ref_clk", "gt_crx_ref_clk";
145    };
146...