ti,mux-clock.yaml

  1# SPDX-License-Identifier: GPL-2.0-only
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Texas Instruments mux clock
  8
  9maintainers:
 10  - Tero Kristo <kristo@kernel.org>
 11
 12description: |
 13  This clock assumes a register-mapped multiplexer with multiple inpt clock
 14  signals or parents, one of which can be selected as output. This clock does
 15  not gate or adjust the parent rate via a divider or multiplier.
 16
 17  By default the "clocks" property lists the parents in the same order
 18  as they are programmed into the register.  E.g:
 19
 20    clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
 21
 22  Results in programming the register as follows:
 23
 24  register value   selected parent clock
 25  0                foo_clock
 26  1                bar_clock
 27  2                baz_clock
 28
 29  Some clock controller IPs do not allow a value of zero to be programmed
 30  into the register, instead indexing begins at 1.  The optional property
 31  "index-starts-at-one" modified the scheme as follows:
 32
 33  register value   selected clock parent
 34  1                foo_clock
 35  2                bar_clock
 36  3                baz_clock
 37
 38  The binding must provide the register to control the mux. Optionally
 39  the number of bits to shift the control field in the register can be
 40  supplied. If the shift value is missing it is the same as supplying
 41  a zero shift.
 42
 43properties:
 44  compatible:
 45    enum:
 46      - ti,mux-clock
 47      - ti,composite-mux-clock
 48
 49  "#clock-cells":
 50    const: 0
 51
 52  clocks: true
 53
 54  clock-output-names:
 55    maxItems: 1
 56
 57  reg:
 58    maxItems: 1
 59
 60  ti,bit-shift:
 61    $ref: /schemas/types.yaml#/definitions/uint32
 62    description:
 63      Number of bits to shift the bit-mask
 64    maximum: 31
 65    default: 0
 66
 67  ti,index-starts-at-one:
 68    type: boolean
 69    description:
 70      Valid input select programming starts at 1, not zero
 71
 72  ti,set-rate-parent:
 73    type: boolean
 74    description:
 75      clk_set_rate is propagated to parent clock,
 76      not supported by the composite-mux-clock subtype.
 77
 78  ti,latch-bit:
 79    $ref: /schemas/types.yaml#/definitions/uint32
 80    description:
 81      Latch the mux value to HW, only needed if the register
 82      access requires this. As an example, dra7x DPLL_GMAC H14 muxing
 83      implements such behavior.
 84    maximum: 31
 85
 86if:
 87  properties:
 88    compatible:
 89      contains:
 90        const: ti,composite-mux-clock
 91then:
 92  properties:
 93    ti,set-rate-parent: false
 94
 95required:
 96  - compatible
 97  - "#clock-cells"
 98  - clocks
 99  - reg
100
101additionalProperties: false
102
103examples:
104  - |
105    bus {
106      #address-cells = <1>;
107      #size-cells = <0>;
108
109      clock-controller@110 {
110        compatible = "ti,mux-clock";
111        reg = <0x0110>;
112        #clock-cells = <0>;
113        clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>;
114        ti,index-starts-at-one;
115        ti,set-rate-parent;
116      };
117
118      clock-controller@120 {
119        compatible = "ti,composite-mux-clock";
120        reg = <0x0120>;
121        #clock-cells = <0>;
122        clocks = <&core_96m_fck>, <&mcbsp_clks>;
123        ti,bit-shift = <4>;
124      };
125    };