ti,cdce925.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/clock/ti,cdce925.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: TI CDCE913/925/937/949 programmable I2C clock synthesizers
  8
  9maintainers:
 10  - Alexander Stein <alexander.stein@ew.tq-group.com>
 11
 12description: |
 13  Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction
 14
 15  - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
 16  - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
 17  - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
 18  - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
 19
 20properties:
 21  compatible:
 22    enum:
 23      - ti,cdce913
 24      - ti,cdce925
 25      - ti,cdce937
 26      - ti,cdce949
 27
 28  reg:
 29    maxItems: 1
 30
 31  clocks:
 32    items:
 33      - description: fixed parent clock
 34
 35  "#clock-cells":
 36    const: 1
 37
 38  vdd-supply:
 39    description: Regulator that provides 1.8V Vdd power supply
 40
 41  vddout-supply:
 42    description: |
 43      Regulator that provides Vddout power supply.
 44      non-L variant: 2.5V or 3.3V for
 45      L variant: 1.8V for
 46
 47  xtal-load-pf:
 48    $ref: /schemas/types.yaml#/definitions/uint32
 49    description: |
 50      Crystal load-capacitor value to fine-tune performance on a
 51      board, or to compensate for external influences.
 52
 53patternProperties:
 54  "^PLL[1-4]$":
 55    type: object
 56    description: |
 57      optional child node can be used to specify spread
 58      spectrum clocking parameters for a board
 59
 60    additionalProperties: false
 61
 62    properties:
 63      spread-spectrum:
 64        $ref: /schemas/types.yaml#/definitions/uint32
 65        description: SSC mode as defined in the data sheet
 66
 67      spread-spectrum-center:
 68        type: boolean
 69        description: |
 70          Use "centered" mode instead of "max" mode. When
 71          present, the clock runs at the requested frequency on average.
 72          Otherwise the requested frequency is the maximum value of the
 73          SCC range.
 74
 75required:
 76  - compatible
 77  - reg
 78  - clocks
 79  - "#clock-cells"
 80
 81additionalProperties: false
 82
 83examples:
 84  - |
 85    i2c {
 86        #address-cells = <1>;
 87        #size-cells = <0>;
 88
 89        cdce925: clock-controller@64 {
 90            compatible = "ti,cdce925";
 91            reg = <0x64>;
 92            clocks = <&xtal_27Mhz>;
 93            #clock-cells = <1>;
 94            xtal-load-pf = <5>;
 95            vdd-supply = <&reg_1v8>;
 96            vddout-supply = <&reg_3v3>;
 97            /* PLL options to get SSC 1% centered */
 98            PLL2 {
 99                spread-spectrum = <4>;
100                spread-spectrum-center;
101            };
102        };
103    };